公开(公告)号：US20210304682A1

公开(公告)日：2021-09-30

申请号：US17196759

申请日：2021-03-09

Applicant: Apple Inc.

Inventor： Bilin Wang ,  Tien-Chien Kuo ,  Kanghoon Jeon ,  Chun-Yao Huang

IPC: G09G3/3291 ,  G09G3/36 ,  G09G5/397

Abstract: A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

公开(公告)号：US20190180672A1

公开(公告)日：2019-06-13

申请号：US16325260

申请日：2017-08-15

Applicant: Apple Inc.

Inventor： Ivan Knez ,  Cheuk Chi Lo ,  Akira Matsudaira ,  Chun-Yao Huang ,  Giovanni Carbone ,  Paolo Sacchetto ,  Chaohao Wang ,  Sheng Zhang ,  Adam Adjiwibawa

IPC: G09G3/20 ,  G09G5/391 ,  G09G5/36 ,  G09G5/397

Abstract: An electronic device may have a display and a gaze tracking system. The electronic device may display images on the display that have a higher resolution in a portion of the display that overlaps a gaze location than other portions of the display. Timing controller circuitry and column driver circuitry may include interpolation and filter circuitry. The interpolation and filter circuitry may be used to perform nearest neighbor interpolation and two-dimensional spatial filtering on low resolution image data. Display driver circuitry may be configured to load higher resolution data into selected portions of a display. The display driver circuitry may include low and high resolution image data buffers and configurable row driver circuitry. Block enable transistors may be included in a display to allow selected blocks of pixels to be loaded with high resolution image data.

公开(公告)号：US10210830B2

公开(公告)日：2019-02-19

申请号：US15631410

申请日：2017-06-23

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Szu-Hsien Lee ,  Kyung-Wook Kim ,  Shih Chang Chang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G09G3/36 ,  G02F1/1368 ,  G02F1/1362 ,  H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  G02F1/1345 ,  G06F3/041 ,  G06F3/044 ,  G09F9/30 ,  G02F1/1333 ,  G02F1/1343

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

公开(公告)号：US10170072B2

公开(公告)日：2019-01-01

申请号：US14860397

申请日：2015-09-21

Applicant: APPLE INC.

Inventor： Byung Duk Yang ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Patrick B. Bennett ,  Shih Chang Chang ,  Wonjae Choi ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Xinyu Zhu

IPC: G09G5/00 ,  G09G3/20 ,  G02F1/1345

Abstract: A display device may include pixels and source lines that provide data line signals to the pixels. The display device may also include gate lines that provide gate signals to switches associated with the pixels. The display device may also include vertical gate lines disposed generally parallel to the source lines and coupled to the gate lines at cross point nodes. The display device may also include compensation lines, such that each compensation line is proximate to a respective vertical gate line. The compensation lines may transmit compensation signals having an opposite polarity as compared to respective gate signals to reduce or eliminate a kickback voltage on at least one of the plurality of pixels.

公开(公告)号：US09847070B2

公开(公告)日：2017-12-19

申请号：US14520797

申请日：2014-10-22

Applicant: Apple Inc.

Inventor： Kwang Soon Park ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: G09G3/36 ,  G06F3/041 ,  G11C19/18

CPC classification number: G09G3/3688 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0294 ,  G09G2310/063 ,  G09G2310/065 ,  G09G2310/08 ,  G09G2320/0209 ,  G11C19/184

Abstract: A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.

公开(公告)号：US09606382B2

公开(公告)日：2017-03-28

申请号：US14712311

申请日：2015-05-14

Applicant: Apple Inc.

Inventor： Young-Jik Jo ,  Chun-Yao Huang ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Shih Chang Chang

IPC: G09G3/34 ,  G02F1/133 ,  G02F1/1343

CPC classification number: G02F1/13306 ,  G02F1/134336 ,  G09G3/3655

Abstract: A display has an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The pixels may be liquid crystal display pixels. Each pixel may have a common electrode voltage terminal. The display may have a transparent conductive film that forms a common electrode voltage layer that overlaps that array and that is shorted to the common electrode voltage terminals of the pixels. Metal common electrode voltage lines may run across the transparent conductive film to reduce resistance. Metal common electrode voltage paths that are coupled to the metal common electrode voltage lines may run along the left and right edge of the display. Common electrode voltage compensation circuits may receive feedback from the metal common electrode voltage paths. There may be two or more common electrode voltage compensation circuits for both the left and right edges of the display.

公开(公告)号：US20170084247A1

公开(公告)日：2017-03-23

申请号：US14860397

申请日：2015-09-21

Applicant: APPLE INC.

Inventor： Byung Duk Yang ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Patrick B. Bennett ,  Shih Chang Chang ,  Wonjae Choi ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Xinyu Zhu

IPC: G09G5/00

CPC classification number: G09G5/003 ,  G02F2001/13456 ,  G09G3/20 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2310/0278 ,  G09G2310/0281 ,  G09G2320/0204 ,  G09G2320/0209 ,  G09G2320/0219 ,  G09G2330/021

Abstract: A display device may include pixels and source lines that provide data line signals to the pixels. The display device may also include gate lines that provide gate signals to switches associated with the pixels. The display device may also include vertical gate lines disposed generally parallel to the source lines and coupled to the gate lines at cross point nodes. The display device may also include compensation lines, such that each compensation line is proximate to a respective vertical gate line. The compensation lines may transmit compensation signals having an opposite polarity as compared to respective gate signals to reduce or eliminate a kickback voltage on at least one of the plurality of pixels.

公开(公告)号：US20170084214A1

公开(公告)日：2017-03-23

申请号：US15162974

申请日：2016-05-24

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chun-Yao Huang ,  Hao-Lin Chiu ,  Ivan Knez ,  Patrick B. Bennett ,  Shih Chang Chang ,  Byung Duk Yang

IPC: G09G3/20 ,  H01L27/12

CPC classification number: G09G3/20 ,  G02F1/136286 ,  G02F2001/13456 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2300/08 ,  G09G2310/0278 ,  G09G2310/0281 ,  G09G2320/0209 ,  G09G2320/0219 ,  H01L27/124

Abstract: A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

公开(公告)号：US09557840B2

公开(公告)日：2017-01-31

申请号：US14489338

申请日：2014-09-17

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G06F3/041

CPC classification number: G06F3/0412 ,  G06F3/0416

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Abstract translation: 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 显示器可以具有帧内暂停（IFP）能力，其中可以在一个或多个帧内消隐间隔期间执行触摸或其它操作。 在一种合适的布置中，栅极驱动电路可以包括多个栅极线驱动器段，每个栅驱动器段由单独的栅极起始脉冲激活。 每个栅极起始脉冲只能在IFP间隔结束时释放。 在另一种合适的布置中，虚拟栅极驱动器单元可插入有源栅极驱动器单元中。 栅极输出信号可能在IFP内部传播通过虚拟栅极驱动器单元。 在另一种合适的布置中，每个有源栅极驱动器单元可以设置有缓冲部分，其保护栅极驱动器单元中的至少一些晶体管免受不期望的应力。

公开(公告)号：US20160118011A1

公开(公告)日：2016-04-28

申请号：US14520797

申请日：2014-10-22

Applicant: Apple Inc.

Inventor： Kwang Soon Park ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: G09G3/36 ,  G06F3/041

CPC classification number: G09G3/3688 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0294 ,  G09G2310/063 ,  G09G2310/065 ,  G09G2310/08 ,  G09G2320/0209 ,  G11C19/184

Abstract: A display may have an array of pixels to display images. Gate line driver circuitry may have stages that supply gate line signals. A gate line may be located in each row of the pixels. Each stage may have an output block that produces a respective one of the gate line signals and may have a carry block that separately produces a carry signal that is provided to a later stage in the gate line driver circuitry. A memory may be provided in at least some of the stages to store signals produced by the output blocks during intraframe pausing operations. At the end of an intraframe pause, the stored signals may be used in restarting production of the gate line signals by output blocks in the gate line driver stages. Circuitry may be used to separately reset the output block and suppress carry signal production by the carry block.

Abstract translation: 显示器可以具有用于显示图像的像素阵列。 栅极线驱动器电路可以具有提供栅极线信号的级。 栅极线可以位于像素的每一行中。 每个级可以具有产生栅极线信号中的相应一个的输出块，并且可以具有分别产生提供给栅极线驱动器电路中的较后级的进位信号的进位块。 可以在至少一些级中提供存储器，以在帧内暂停操作期间存储由输出块产生的信号。 在帧内暂停结束时，存储的信号可以用于通过栅极线驱动器级中的输出块重新开始生成栅极线信号。 可以使用电路来单独复位输出块，并抑制进位块的进位信号产生。