公开(公告)号：US08669828B1

公开(公告)日：2014-03-11

申请号：US12909739

申请日：2010-10-21

申请人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

发明人： Wilson Wong ,  Allen Chan ,  Sergey Shumarayev

IPC分类号： H04B3/28

CPC分类号： H01L23/642 ,  H01L2924/0002 ,  H05K1/0231 ,  H01L2924/00

摘要： Integrated circuits with decoupling capacitor circuitry are provided. Decoupling capacitor circuitry may include multiple arrays of decoupling capacitors. Each decoupling capacitor array may have a corresponding decoupling capacitor monitoring circuit that is associated with that decoupling capacitor array. Each decoupling capacitor monitoring circuit may include a resistor and switching circuitry. Each decoupling capacitor monitoring circuit may be coupled to a comparator and control circuitry. During testing, the control circuitry may configure each decoupling capacitor array for leakage current testing one at a time. If a decoupling capacitor array is determined to exhibit excessive leakage currents, that decoupling capacitor array will be marked as defective and will be disabled from use. If the decoupling capacitor array is determined to exhibit tolerable leakage currents, that decoupling capacitor array will be enable for use to help reduce power supply noise.

摘要翻译： 提供具有去耦电容电路的集成电路。 去耦电容器电路可以包括多个去耦电容器阵列。 每个去耦电容器阵列可以具有与该去耦电容器阵列相关联的相应的去耦电容器监控电路。 每个去耦电容器监控电路可以包括电阻器和开关电路。 每个去耦电容器监控电路可以耦合到比较器和控制电路。 在测试期间，控制电路可以配置每个去耦电容器阵列以便一次一个地进行漏电流测试。 如果解耦电容器阵列被确定为表现出过多的漏电流，则该去耦电容阵列将被标记为有缺陷的并且将被禁止使用。 如果解耦电容器阵列被确定为表现出可容忍的漏电流，则该去耦电容器阵列将被用于帮助减少电源噪声。

公开(公告)号：US08537954B2

公开(公告)日：2013-09-17

申请号：US12688617

申请日：2010-01-15

申请人： Sergey Y. Shumarayev ,  Rakesh H. Patel ,  Wilson Wong ,  Tim T. Hoang

发明人： Sergey Y. Shumarayev ,  Rakesh H. Patel ,  Wilson Wong ,  Tim T. Hoang

IPC分类号： H03D3/24

CPC分类号： H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

摘要翻译： 所公开的发明是使用容纳灵活范围操作频率F和连续相同数字要求CID的多模式时钟数据恢复（CDR）电路产生恢复的时钟信号的技术。 在第一操作模式中，受控振荡器产生恢复的时钟信号，并且在第二操作模式中，相位内插器产生恢复的时钟信号。 （CID / F）小于阈值时间值，如果（CID / F）大于阈值时间值，则多模式CDR电路以第一模式工作。

公开(公告)号：US08189729B2

公开(公告)日：2012-05-29

申请号：US11329197

申请日：2006-01-09

申请人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

发明人： Tim Tri Hoang ,  Sergey Yuryevich Shumarayev ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H03K19/17732 ,  H03K19/17744 ,  H03L7/10 ,  H04L7/0004 ,  H04L7/033

摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.

摘要翻译： 宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。 为了支持广泛的数据速率，CDR架构包括多个操作参数。 这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。 可以在不关闭电路或PLD的情况下动态重新编程参数。 这允许CDR电路在各种标准和协议之间进行即时切换。

公开(公告)号：US08175143B1

公开(公告)日：2012-05-08

申请号：US12037284

申请日：2008-02-26

申请人： Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

发明人： Wilson Wong ,  Tin H. Lai ,  Allen Chan ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC分类号： H03H7/30

CPC分类号： H04L25/03057 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03745 ,  H04L2025/03783

摘要： A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.

摘要翻译： 用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机 以提取用于数字化的参考电平并控制均衡曲线。 参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。 状态机优选是可编程的。 这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

公开(公告)号：US08127215B2

公开(公告)日：2012-02-28

申请号：US13151717

申请日：2011-06-02

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03M13/03

CPC分类号： H04L25/45

摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US08111784B1

公开(公告)日：2012-02-07

申请号：US12082483

申请日：2008-04-11

申请人： Weiqi Ding ,  Mingde Pan ,  Wilson Wong ,  Sergey Shumarayev ,  Peng Li

发明人： Weiqi Ding ,  Mingde Pan ,  Wilson Wong ,  Sergey Shumarayev ,  Peng Li

IPC分类号： H04L25/06

CPC分类号： H04L25/063

摘要： Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.

摘要翻译： 用于收集关于高速串行数据信号的眼睛的信息的方法和装置包括在几个眼睛切片位置采样重复的多位数据模式的每一位。 对于任何给定的眼片位置，将数据模式中的每个位在电压中与基线参考信号电压进行比较，以建立该位的参考值。 然后在重复电压比较时，参考信号电压逐渐增加，直到比较结果的一些位与该位的参考值不同。 这在眼部切片位置建立了眼睛的上限值。 然后，参考信号电压逐渐减小，以类似地找到该眼片的较低值。

公开(公告)号：US20110211621A1

公开(公告)日：2011-09-01

申请号：US13103132

申请日：2011-05-09

申请人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Bill W. Bereza ,  Chong H. Lee ,  Rakesh H. Patel ,  Wilson Wong

IPC分类号： H04L5/14 ,  H04L27/00

CPC分类号： H04L5/14 ,  H03K19/17744 ,  H04L27/00

摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

摘要翻译： 可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道 达到第二个相对较高的最大数据速率。 相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。 相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

公开(公告)号：US07924184B1

公开(公告)日：2011-04-12

申请号：US11904008

申请日：2007-09-24

申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

IPC分类号： H03M9/00

CPC分类号： H03K19/1732

摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.

摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和高速串行数据信号接口（例如，收发器）电路的通道。 为了使集成电路能够支持许多可能的不同高速串行通信协议中的任何一种，该信道被硬接线以包括用于与可编程电路交换并行数据的固定宽度的并行数据总线。 无论正在执行协议，始终使用该总线的全宽。 可编程电路的一部分被编程为在块宽度和组宽度之间转换数据，其可以与块宽度不同，并且用于集成电路中其他地方的数据。

公开(公告)号：US07920621B2

公开(公告)日：2011-04-05

申请号：US11522284

申请日：2006-09-14

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US07821343B1

公开(公告)日：2010-10-26

申请号：US12229813

申请日：2008-08-27

申请人： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

发明人： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

IPC分类号： H03L7/00

CPC分类号： H03L7/23

摘要： A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.

摘要翻译： 描述了包括耦合到第一PLL的第一锁相环（PLL）和第二PLL的发射机。 在一个实现中，第一PLL是电感 - 电容（LC）型PLL，第二PLL是环型PLL。 此外，在一个实施例中，发射机还包括耦合到第一和第二PLL的PLL选择多路复用器，其中PLL选择多路复用器接收第一PLL的输出和第二PLL的输出，并输出第一PLL的输出 或第二PLL的输出。 在一个实现中，用于控制PLL选择多路复用器的选择的控制信号在运行时可编程。 在一个实现中，本发明的发射机还包括耦合到PLL选择多路复用器的时钟产生模块，耦合到时钟产生模块的串行器模块和耦合到串行器模块的发送驱动器模块。 在一个实施例中，发射驱动器块仅包括一个抽头前驱动器和仅一个主抽头预驱动器。 本发明的发射机能够通过选择适当的PLL在宽范围模式或低抖动模式下工作。 在宽范围模式下，需要较宽的频率范围。 另一方面，在低抖动模式中，需要低抖动。