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210 条记录 (耗时 0.037 秒)

    Method and apparatus for protecting a circuit during a hot socket condition
    61.
    发明申请
    Method and apparatus for protecting a circuit during a hot socket condition 有权
    在热插座状态下保护电路的方法和装置

    公开(公告)号：US20070115028A1

    公开(公告)日：2007-05-24

    申请号：US11251099

    申请日：2005-10-14

    申请人： Xiaobao Wang ,  Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang

    发明人： Xiaobao Wang ,  Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang

    IPC分类号： H03K19/00

    CPC分类号： H03K19/00315

    摘要： The hot socket detect circuit of the present invention includes a well bias circuit and three hot socket detect blocks. If the output of any of the three hot socket detect blocks is a digital high signal then the output of the hot socket detect circuit is a digital high signal. The digital high signal indicates that a hot socket condition exists.

    摘要翻译： 本发明的热插座检测电路包括阱偏置电路和三个热插座检测块。 如果三个热插座检测块中的任一个的输出是数字高信号，则热插座检测电路的输出是数字高电平信号。 数字高电平信号表示存在热插座状况。

    Programmable I/O element circuit for high speed logic devices
    64.
    发明申请
    Programmable I/O element circuit for high speed logic devices 有权
    用于高速逻辑器件的可编程I / O元件电路

    公开(公告)号：US20050162187A1

    公开(公告)日：2005-07-28

    申请号：US11025774

    申请日：2004-12-29

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Phillip Pan ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Xiaobao Wang ,  Tzung-Chin Chang

    IPC分类号： C07K14/47 ,  C07K16/28 ,  H03K19/177

    CPC分类号： C07K16/28 ,  A61K2039/505 ,  C07K14/47

    摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed I/O modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

    摘要翻译： 用于逻辑阵列的I / O端子的可编程I / O元件适用于根据双速数据速率和零总线周转等高速I / O模式进行工作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。 另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。 对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块为输出缓冲器的选通输入提供使能信号。 可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

    Schmitt trigger circuit with adjustable trip point voltages
    65.
    发明授权
    Schmitt trigger circuit with adjustable trip point voltages 有权
    施密特触发电路具有可调跳闸点电压

    公开(公告)号：US06870413B1

    公开(公告)日：2005-03-22

    申请号：US10017933

    申请日：2001-12-14

    申请人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    发明人： Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Yan Chong ,  Xiaobao Wang ,  Philip Pan ,  Gopinath Rangan ,  In Whan Kim

    IPC分类号： H03K3/3565 ,  H03K3/012

    CPC分类号： H03K3/3565

    摘要： A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

    摘要翻译： 施密特触发电路具有可调滞后特性，通过提供多个反馈电路，其不同地影响电路的上跳点电平和较低跳变点电平的至少一个，优选两者。 可以通过从第一组反馈电路中选择所需的反馈电路来调整上跳点电平，和/或可以通过从第二组反馈电路中选择所需的反馈电路来调整下跳变点电平。 反馈电路选择由一个或多个可编程的控制信号来实现。 可以调节滞后特性，以满足不同VCC电平下的所需噪声容限，延迟和输入识别准则。 施密特触发电路可以是具有两个输入级NMOS，两个输入级PMOS晶体管，第一组NMOS反馈电路组和第二组PMOS反馈电路的CMOS施密特触发器。

    Dual-port SRAM in a programmable logic device
    67.
    发明授权
    Dual-port SRAM in a programmable logic device 有权
    可编程逻辑器件中的双端口SRAM

    公开(公告)号：US06661733B1

    公开(公告)日：2003-12-09

    申请号：US09883087

    申请日：2001-06-15

    申请人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

    发明人： Philip Y. Pan ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Gopinath Rangan ,  In Whan Kim ,  Yan Chong

    IPC分类号： G11C800

    CPC分类号： H03K19/1776 ,  G11C8/16

    摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

    摘要翻译： 可编程逻辑器件中双端口SRAM的方法和装置。 一个实施例提供了包括双端口存储器的可编程逻辑集成电路。 存储器包括多个存储器存储单元，并且每个存储器存储单元具有具有第一节点和第二节点的存储单元，连接在第一数据线和存储器单元的第一节点之间的第一系列器件，以及 连接在第二数据线和存储器单元的第二节点之间的第二系列器件。 读单元连接到存储单元的第二节点。 字线连接到第一系列设备中的第一设备，第二系列设备中的第二设备和读取单元。

    Technique to test an integrated circuit using fewer pins
    68.
    发明授权
    Technique to test an integrated circuit using fewer pins 有权
    使用较少引脚测试集成电路的技术

    公开(公告)号：US06538469B1

    公开(公告)日：2003-03-25

    申请号：US09630071

    申请日：2000-07-31

    申请人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Xiaobao Wang

    发明人： Khai Nguyen ,  Chiakang Sung ,  Bonnie Wang ,  Joseph Huang ,  Xiaobao Wang

    IPC分类号： H03K19177

    CPC分类号： H03K19/17764 ,  G01R31/318516 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744

    摘要： A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this permits downbonding of the integrated circuit into a package with fewer pins. This technique may be used to implement test Functions in a programmable logic device. Test data may be serially input using a test pin (410) for two or more columns (320) of logic blocks. The test data is stored in an A resister (330), and may be later transferred into a B register (335).

    摘要翻译： 实现需要较少的集成电路引脚的功能以将数据串行传输到用于多个逻辑块的集成电路的技术。 通过减少所需的引脚，可以将集成电路下降到具有较少引脚的封装中。 该技术可用于在可编程逻辑器件中实现测试功能。 可以使用针对逻辑块的两列或多列（320）的测试引脚（410）来串行输入测试数据。 测试数据存储在A寄存器（330）中，并且可以稍后传送到B寄存器（335）。

    Configurable input-output (I/O) circuitry with pre-emphasis circuitry
    69.
    发明授权
    Configurable input-output (I/O) circuitry with pre-emphasis circuitry 有权
    具有预加重电路的可组态输入输出（I / O）电路

    公开(公告)号：US08390315B1

    公开(公告)日：2013-03-05

    申请号：US13354780

    申请日：2012-01-20

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

    IPC分类号： H03K19/013 ,  H03K17/16

    CPC分类号： H03K19/01721 ,  H03K19/018571

    摘要： Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.

    摘要翻译： 公开了具有可配置的输入 - 输出电路来操作集成电路（IC）的电路和技术。 所公开的电路包括耦合到输出端子的单端输入 - 输出缓冲器。 单端输入 - 输出缓冲器可用于将输入信号作为输出信号发送到输出端。 用于锐化输出信号的第一边缘和第二边缘的预加重电路耦合在单端输入 - 输出缓冲器和输出端子之间。 当输入信号从第一逻辑电平切换到第二逻辑电平时，输出信号的第一边缘被锐化，而当输入信号从第二逻辑电平切换到第一逻辑电平时，输出信号的第二边沿被锐化。

    Level shifter circuits and methods
    70.
    发明授权
    Level shifter circuits and methods 有权
    电平移位电路和方法

    公开(公告)号：US07994821B1

    公开(公告)日：2011-08-09

    申请号：US12753389

    申请日：2010-04-02

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

    IPC分类号： H03K19/0175

    CPC分类号： H03K3/356069

    摘要： A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.

    摘要翻译： 电平移位器电路包括串联耦合的第一和第二晶体管，以及串联耦合的第三和第四晶体管。 第四晶体管耦合到第一和第二晶体管之间的第一节点。 电平移位器电路还包括串联耦合的第五和第六晶体管，以及串联耦合的第七和第八晶体管。 第八晶体管耦合到第五和第六晶体管之间的第二节点。 第二和第八晶体管在控制输入端接收第一输入信号。 第四和第六晶体管在控制输入端接收第二输入信号。 第二输入信号相对于第一输入信号反相。