Abstract:
An immersion lithography apparatus includes a lens assembly having an imaging lens, a wafer stage for securing a wafer beneath the lens assembly, a fluid module for providing a fluid into a space between the lens assembly and the wafer, and a plurality of extraction units positioned proximate to an edge of the wafer. The extraction units are configured to operate independently to remove a portion of the fluid provided into the space between the lens assembly and the wafer.
Abstract:
An immersion lithography resist material comprising a matrix polymer having a first polarity and an additive having a second polarity that is substantially greater than the first polarity. The additive may have a molecular weight that is less than about 1000 Dalton. The immersion lithography resist material may have a contact angle that is substantially greater than the contact angle of the matrix polymer.
Abstract:
A method for immersion lithography includes providing a substrate coated with an imaging layer, dispensing a conductive immersion fluid between the substrate and an imaging lens of a lithography system, and performing an exposure process to the imaging layer using a radiation energy through the conductive immersion fluid.
Abstract:
A method for cleaning a photomask includes cleaning the photomask with a chemical cleaner, introducing a solution to the photomask, the solution is configured to react with residuals generated from the chemical cleaner to form insoluble precipitates, and rinsing the photomask with a fluid to remove the insoluble precipitates from the photomask.
Abstract:
A method of forming a resist pattern in a semiconductor device layer includes forming a buffer layer on a semiconductor device layer and forming a resist layer on the buffer layer. A decomposing agent is released into a portion of the buffer layer by a portion of the resist layer whereupon the portion of the buffer layer and the portion of the resist layer are removed to form a process window substantially free of resist residue that can be subsequently exploited for etching of the semiconductor device layer.
Abstract:
An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.
Abstract:
An ESD-resistant photomask and method of preventing mask ESD damage is disclosed. The ESD-resistant photomask includes a mask substrate, a pattern-forming material provided on the substrate, a circuit pattern defined by exposure regions etched in the pattern-forming material, and positive or negative ions implanted into the mask substrate throughout ion implantation regions. The ions in the ion implantation regions dissipate electrostatic charges on the mask, thus preventing the buildup of electrostatic charges which could otherwise attract image-distorting particles to the mask or damage the mask.
Abstract:
A megasonic immersion lithography exposure apparatus and method for substantially eliminating microbubbles from an exposure liquid in immersion lithography is disclosed. The apparatus includes an optical system for projecting light through a mask and onto a wafer.An optical transfer chamber is provided adjacent to the optical system for containing an exposure liquid. At least one megasonic plate operably engages the optical transfer chamber for inducing sonic waves in and eliminating microbubbles from the exposure liquid.
Abstract:
An optical proximity correction photomask comprises a transparent substrate, a main feature having a first transmitivity disposed on the transparent substrate and at least one assist feature having a second transmitivity disposed beside the main feature and on the transparent substrate, wherein the first transmitivity is not equal to the second transmitivity.
Abstract:
An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on the first layer. Portions of the second and/or third layer are selectively removed from regions in and around the first overlay mark. A second overlay mark is formed and aligned to the first overlay mark. The alignment between the second overlay mark and first overlay mark may be measured with an attenuated error due to reflection and refraction or due to an edge profile shift of the first overlay mark.