公开(公告)号：US07482649B2

公开(公告)日：2009-01-27

申请号：US11335390

申请日：2006-01-19

申请人： Sung-Min Kim ,  Eun-Jung Yun

发明人： Sung-Min Kim ,  Eun-Jung Yun

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/0692 ,  H01L29/7923

摘要： Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall and a lower surface of the recess region. A gate electrode is on the insulating layer in the recessed region. At least one pair of impurity regions are in the semiconductor substrate. The impurity regions adjoin a side surface of the insulating layer in the recess region and form a relative angle that is less than 120° therebetween with respect to a center of the gate electrode.

摘要翻译： 描述了多位非易失性存储器件及其相关制造方法。 在一些多位非易失性存储器件中，半导体衬底具有限定在其中的凹陷区域。 可以包括ONO层的绝缘层被配置为在其中的编程区域内存储数据，并且覆盖凹部区域的侧壁和下表面。 栅电极位于凹陷区域的绝缘层上。 半导体衬底中至少有一对杂质区。 杂质区域与凹陷区域中的绝缘层的侧表面相邻，并且相对于栅电极的中心形成小于120°的相对角度。

公开(公告)号：US07285456B2

公开(公告)日：2007-10-23

申请号：US11295770

申请日：2005-12-07

申请人： Sung-Min Kim ,  Eun-Jung Yun

发明人： Sung-Min Kim ,  Eun-Jung Yun

IPC分类号： H01L21/8238

CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795

摘要： In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming a source and drain region in a portion of the active region pattern, forming a plurality of vertically protruding channels between the source and drain region, forming a gate dielectric layer on the active region pattern having the plurality of protruding channels, and forming a gate electrode on the gate dielectric layer.

摘要翻译： 在制造具有多个突出通道的鳍状场效应晶体管的方法中，通过在第一硬掩模图案上形成伪栅极图案和在具有有源区域图案的半导体衬底上形成第一绝缘层来形成鳍状场效应晶体管 在所述有源区域图案的一部分中形成源极和漏极区域，在所述源极和漏极区域之间形成多个垂直突出的沟道，在所述有源区域图案上形成具有所述多个突出沟道的栅极电介质层， 栅极电介质层上的栅电极。

公开(公告)号：US20070111487A1

公开(公告)日：2007-05-17

申请号：US11600719

申请日：2006-11-17

申请人： Sung-Min Kim ,  Eun-Jung Yun

发明人： Sung-Min Kim ,  Eun-Jung Yun

IPC分类号： H01L21/20

CPC分类号： H01L27/24

摘要： A method of fabricating a semiconductor device includes sequentially forming a first pattern and a second pattern on a substrate, the second pattern being a non-single-crystalline semiconductor stacked on the first pattern, wherein a portion of the substrate is exposed adjacent to the first and second patterns, forming a non-single-crystalline semiconductor layer on the substrate, the semiconductor layer contacting the second pattern and the exposed portion of the substrate, and, using the substrate as a seed layer, changing the crystalline state of the semiconductor layer to be single-crystalline and changing the crystalline state of the second pattern to be single-crystalline.

摘要翻译： 一种制造半导体器件的方法包括在衬底上顺序地形成第一图案和第二图案，第二图案是堆叠在第一图案上的非单晶半导体，其中衬底的一部分暴露在与第一图案相邻的第一图案 和第二图案，在衬底上形成非单晶半导体层，与第二图案接触的半导体层和衬底的暴露部分，并且使用衬底作为种子层，改变半导体层的结晶状态 为单晶，并将第二图案的结晶状态改变为单晶。

公开(公告)号：US07129541B2

公开(公告)日：2006-10-31

申请号：US10945246

申请日：2004-09-20

申请人： Sung-Min Kim ,  Hye-Jin Cho ,  Shin-Ae Lee ,  Eun-Jung Yun ,  Dong-Gun Park

发明人： Sung-Min Kim ,  Hye-Jin Cho ,  Shin-Ae Lee ,  Eun-Jung Yun ,  Dong-Gun Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L3/113 ,  H01L31/119

CPC分类号： H01L29/78696 ,  H01L29/42336 ,  H01L29/42384 ,  H01L29/66787 ,  H01L29/66825

摘要： A field effect transistor on an active region of a semiconductor substrate includes a vertically protruding thin-body portion of the semiconductor substrate and a vertically oriented gate electrode at least partially inside a cavity defined by opposing sidewalls of the vertically protruding portion of the substrate. The transistor further includes an insulating layer surrounding an upper portion of the vertically oriented gate electrode and a laterally oriented gate electrode on the insulating layer and connected to a top portion of the vertically oriented gate electrode. Accordingly, a T-shaped gate electrode is defined having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of a vertically protruding portion of the substrate.

摘要翻译： 在半导体衬底的有源区域上的场效应晶体管包括半导体衬底的垂直突出的薄体部分和至少部分地在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直取向的栅电极。 晶体管还包括围绕垂直取向的栅电极的上部的绝缘层和绝缘层上的横向取向的栅电极，并连接到垂直取向的栅电极的顶部。 因此，T形栅电极被限定为具有在半导体衬底的顶表面上的横向部分，并且具有至少部分至少部分在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直部分。

公开(公告)号：US20060157753A1

公开(公告)日：2006-07-20

申请号：US11335390

申请日：2006-01-19

申请人： Sung-Min Kim ,  Eun-Jung Yun

发明人： Sung-Min Kim ,  Eun-Jung Yun

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/0692 ,  H01L29/7923

摘要： Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall and a lower surface of the recess region. A gate electrode is on the insulating layer in the recessed region. At least one pair of impurity regions are in the semiconductor substrate. The impurity regions adjoin a side surface of the insulating layer in the recess region and form a relative angle that is less than 120° therebetween with respect to a center of the gate electrode.

摘要翻译： 描述了多位非易失性存储器件及其相关制造方法。 在一些多位非易失性存储器件中，半导体衬底具有限定在其中的凹陷区域。 可以包括ONO层的绝缘层被配置为在其中的编程区域内存储数据，并且覆盖凹部区域的侧壁和下表面。 栅电极位于凹陷区域的绝缘层上。 半导体衬底中至少有一对杂质区。 杂质区域与凹陷区域中的绝缘层的侧表面相邻，并且相对于栅电极的中心形成小于120°的相对角度。

公开(公告)号：US20060120148A1

公开(公告)日：2006-06-08

申请号：US11238381

申请日：2005-09-29

申请人： Sung-Min Kim ,  Eun-Jung Yun ,  Jong-Soo Seo ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Byung-Seo Kim

发明人： Sung-Min Kim ,  Eun-Jung Yun ,  Jong-Soo Seo ,  Du-Eung Kim ,  Beak-Hyung Cho ,  Byung-Seo Kim

IPC分类号： G11C11/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

公开(公告)号：US06914316B2

公开(公告)日：2005-07-05

申请号：US10617742

申请日：2003-07-14

申请人： Eun-Jung Yun ,  Sung-Eui Kim

发明人： Eun-Jung Yun ,  Sung-Eui Kim

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/00

CPC分类号： H01L21/76229

摘要： A trench structure of a semiconductor device includes first and second regions of a substrate having first and second trenches, respectively, the first trench having an aspect ratio larger than that of the second trench, a first insulation material on a bottom and sidewalls of the first trench forming a first sub-trench in the first trench, a second insulation material completely filling the first sub-trench, a third insulation material formed on a bottom and sidewalls of the second trench forming a second sub-trench in the second trench, a fourth insulation material formed on a bottom and sidewalls of the second sub-trench, and a fifth insulation material completely filling a third sub-trench formed in the second sub-trench by the fourth insulation material.

摘要翻译： 半导体器件的沟槽结构包括分别具有第一和第二沟槽的衬底的第一和第二区域，第一沟槽的纵横比分别大于第二沟槽的纵横比，第一绝缘材料位于第一和第二沟槽的底部和侧壁上 在所述第一沟槽中形成第一子沟槽的沟槽，完全填充所述第一子沟槽的第二绝缘材料，形成在所述第二沟槽的底部和侧壁上的第三绝缘材料，所述第二沟槽在所述第二沟槽中形成第二子沟槽， 第四绝缘材料形成在第二子沟槽的底部和侧壁上，第五绝缘材料通过第四绝缘材料完全填充形成在第二子沟槽中的第三子沟槽。

公开(公告)号：US06881637B2

公开(公告)日：2005-04-19

申请号：US10672884

申请日：2003-09-26

申请人： Jae-Jong Han ,  Yong-Woo Hyung ,  Seung-Mok Shin ,  Kong-Soo Lee ,  Eun-Jung Yun

发明人： Jae-Jong Han ,  Yong-Woo Hyung ,  Seung-Mok Shin ,  Kong-Soo Lee ,  Eun-Jung Yun

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/28247 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837

摘要： In a method for forming a gate electrode having an excellent sidewall profile, after a gate structure is formed on a substrate, a first oxide film is formed on a sidewall of the gate structure and on the substrate by re-oxidizing the gate structure and the substrate under an atmosphere including an oxygen gas and an inert gas. The gate structure has a gate oxide film pattern, a polysilicon film pattern and a metal silicide film pattern. A portion of the first oxide film formed on a sidewall of the polysilicon film pattern has a thickness substantially identical to that of a portion of the first oxide film formed on a sidewall of the metal silicide film pattern. A failure of a semiconductor device having the gate electrode can be minimized because the gate electrode has an improved sidewall profile.

摘要翻译： 在形成具有优异的侧壁轮廓的栅电极的方法中，在基板上形成栅极结构之后，在栅极结构的侧壁和基板上形成第一氧化膜，通过重新氧化栅极结构和 在包含氧气和惰性气体的气氛下进行。 栅极结构具有栅极氧化膜图案，多晶硅膜图案和金属硅化物膜图案。 形成在多晶硅膜图案的侧壁上的第一氧化膜的一部分的厚度与形成在金属硅化物膜图案的侧壁上的第一氧化物膜的部分的厚度基本相同。 具有栅电极的半导体器件的故障可以最小化，因为栅电极具有改进的侧壁轮廓。