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公开(公告)号：US5635869A
公开(公告)日：1997-06-03
申请号：US536222
申请日：1995-09-29
CPC分类号： G05F3/262
摘要： A constant-current generator circuit includes an output circuit and a control circuit, with the control circuit producing a control voltage to define a reference current through the output circuit. An important feature is that the control circuit uses a pair of transistors having different threshold voltages in generating the control voltage. The circuit is formed using CMOS technology, and the difference in threshold voltage may be produced by doping the polysilicon gate of an N-channel or P-channel field effect transistor. The step of doping to produce the change in threshold voltage is compatible with the standard processing for the CMOS device. In a preferred embodiment, the control circuit uses two pairs of control transistors, each pair having differing thresholds. One pair is P-channel and the other N-channel. These pairs are in parallel, the P-channel pair connected to the positive supply and the N-channel pair to the negative supply or ground. Each pair is connected in a cascode arrangement, producing two control voltages for two symmetrical output transistors in the output circuit, one N-channel and one P-channel.
摘要翻译： 恒流发生器电路包括输出电路和控制电路，控制电路产生控制电压以限定通过输出电路的参考电流。 一个重要的特征是控制电路在产生控制电压时使用具有不同阈值电压的一对晶体管。 该电路使用CMOS技术形成，并且阈值电压的差异可以通过掺杂N沟道或P沟道场效应晶体管的多晶硅栅极产生。 掺杂产生阈值电压变化的步骤与CMOS器件的标准处理兼容。 在优选实施例中，控制电路使用两对控制晶体管，每对控制晶体管具有不同的阈值。 一对是P通道和另一个N通道。 这些对并联，P沟道对连接到正电源，N沟道对连接到负电源或地。 每对以串联布置连接，为输出电路中的两个对称输出晶体管产生两个控制电压，一个N沟道和一个P沟道。
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公开(公告)号：US5598442A
公开(公告)日：1997-01-28
申请号：US261522
申请日：1994-06-17
IPC分类号： G06F13/42 , H04L7/00 , H04L7/02 , H04L7/033 , H04L7/04 , H04L12/56 , H04L25/14 , H04L25/49 , H04L29/06
CPC分类号： H04L29/06 , G06F13/4278 , H04L25/14 , H04L25/4908 , H04L7/041 , H04L2007/045 , H04L69/14 , H04L7/0008
摘要： A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along with its idle and data character sequences. Each of the plurality of bytes is transmitted on a separate conducting line along with a transmit clock signal that is also transmitted on a separate line. At the receiver, the data stream on each line is separately phase aligned with the clock, and bit aligned.
摘要翻译： 自定义接口（STI）链接两个物理上分离的系统或节点。 发送状态机将串行比特流中的每个单词形成多个字节，并生成空闲和数据字符序列。 每个字节分别以游程长度限制的代码及其空闲和数据字符序列编码。 多个字节中的每一个与分离的线路上发送的发送时钟信号一起在单独的导线上发送。 在接收机上，每行上的数据流与时钟分开相位对齐，并且位对齐。
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63.发明授权Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus 失效共享信道子系统具有使用接收到的时钟信号的自定时接口，以对从并行总线接收的位进行单独的相位对准
公开(公告)号：US5522088A
公开(公告)日：1996-05-28
申请号：US261641
申请日：1994-06-17
CPC分类号： G06F13/4022 , G06F13/405
摘要： A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a cost effective, modular input/output element.
摘要翻译： 共享信道子系统具有用于通过自定义接口（STI）将多个输入 - 输出控制器中的每一个耦合到多个处理器节点中的每一个的输入 - 输出元件，其中时钟信号将位串行数据时钟 并行的导电总线，并且时钟信号在总线的单独线路上传输。 总线上每条线上的接收数据与时钟信号单独相位对齐，提供了一个经济有效的模块化输入/输出元件。
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64.发明授权Circuit for converting between serial and parallel data streams by high speed addressing 失效用于通过高速寻址在串行和并行数据流之间转换的电路
公开(公告)号：US4901076A
公开(公告)日：1990-02-13
申请号：US114178
申请日：1987-10-29
申请人： Haluk O. Askin , Frank D. Ferraiolo
发明人： Haluk O. Askin , Frank D. Ferraiolo
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A circuit for converting a multi-bit data signal from a first format to a second format. The circuit includes an input for receiving the multi-bit data signal in a first format, an output for providing the multi-bit data signal in a second format, and a ring counter having a number of stages for providing, in sequential order, stage output signals. A format conversion device connected between the input and the output has a number of latches with each latch being connected to the input for simultaneously receiving data bits of the multi-bit data signal in the first format. A control circuit is provided for controlling the latching of selected data bits in each of the latches, and a transmission circuit is provided between the latches and the output for transmitting the bits latched in the latches to the output responsive to the stage output signals of the ring counter, thereby placing the multi-bit data signal in the second format.
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公开(公告)号：US09325534B2
公开(公告)日：2016-04-26
申请号：US12568765
申请日：2009-09-29
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译： 一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。 控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。 传输幅度和数据的单端或差分传输是功率模式的例子。 控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。
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公开(公告)号：US08862944B2
公开(公告)日：2014-10-14
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright , Lisa C. Gower
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译： 隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法。 检测到错误状况，并且确定错误状况被隔离到单个传输链路。 在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。 如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。
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67.发明申请公开(公告)号：US20140032799A1
公开(公告)日：2014-01-30
申请号：US13561446
申请日：2012-07-30
IPC分类号： G06F13/00
CPC分类号： G06F15/17318 , G06F9/00 , G06F11/3058 , G06F13/00 , G06F13/1673 , G06F13/24 , G06F13/4217 , G06F13/4282 , G06F15/803 , G06F19/00 , H04B1/38 , H04L12/56 , Y02D10/14 , Y02D10/151
摘要： A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.
摘要翻译： 可校准通信链路包括多条平行线。 由自动机制确定的动态变量和/或可中断间隔进行校准。 校准优选地响应于由可执行软件过程产生的命令来启动，该指令响应于可能的即将发生的需求的检测而启动校准，如由温度变化，校准参数漂移，错误率等指示的。也优选地根据 可能的最小的设备功能中断，如低活动水平所示。 此外，在一个方面，可以临时暂停校准以发送数据，然后恢复。
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公开(公告)号：US20110320881A1
公开(公告)日：2011-12-29
申请号：US12822508
申请日：2010-06-24
申请人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
发明人： John S. Dodson , Frank D. Ferraiolo , Michele M. Franceschini , Kevin C. Gower , Lisa C. Gower , Ashish Jagmohan , Luis A. Lastras-Montano , Kenneth L. Wright
IPC分类号： G06F11/34
CPC分类号： G06F11/10 , G06F11/2005 , H04L1/0061 , H04L2001/0096
摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
摘要翻译： 隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法检测到错误状况，并且确定错误状况被隔离为单个 传输链路。 在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。 如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。
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公开(公告)号：US07729153B2
公开(公告)日：2010-06-01
申请号：US12060998
申请日：2008-04-02
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。
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70.发明授权276-Pin buffered memory module with enhanced fault tolerance and a performance-optimized pin assignment 失效276引脚缓冲存储器模块，具有增强的容错能力和性能优化的引脚分配公开(公告)号：US07529112B2
公开(公告)日：2009-05-05
申请号：US11695679
申请日：2007-04-03
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon including a plurality of high-speed bus interface pills arranged on said card for communicating with a plurality of high-speed busses. The high-speed bus interface pins associated with a single high-speed bus are located on one side of the card with respect to a midpoint of the length of the card, thus the pin assignments are defined such that the performance of the DIMM in a system is optimized for high frequency operation.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡包括至少276个引脚，其构造为包括布置在所述卡上的多个高速总线接口卡，用于与多个高速总线通信。 与单个高速总线相关联的高速总线接口引脚相对于卡的长度的中点位于卡的一侧，因此引脚分配被定义为使得DIMM的性能在 系统针对高频操作进行了优化。
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