公开(公告)号：US5636347A

公开(公告)日：1997-06-03

申请号：US733335

申请日：1996-10-17

申请人： Michael J. Muchnick ,  Jerry A. Verseput ,  Jasmin Ajanovic

发明人： Michael J. Muchnick ,  Jerry A. Verseput ,  Jasmin Ajanovic

IPC分类号： G06F13/40 ,  G06K7/00 ,  H05K1/11 ,  G06F13/20

CPC分类号： H05K1/117 ,  G06F13/4072 ,  G06K7/0047 ,  H05K2201/0746 ,  H05K2201/094 ,  H05K2201/10022

摘要： A personal computer (PC) card insertion method and apparatus uses a subset of connector ground terminals and pins, located at either end of the connector, for detecting the onset of a card insertion. The host PC card slot connector has pull-up resistors for keeping the subset of ground terminals at a high logic level (V.sub.CC). Also, the subset of pins are made longer than the signal pins so that when an insertion of a PC card begins, the grounding of one or more of the subset of pins indicates that a PC card insertion has begun, allowing the host system to take the necessary precautions to ensure an orderly acceptance of the card without any undesirable system affects that might otherwise result. Also, a logic network for using the subset of connector terminals as additional grounding connections is provided upon completion of the insertion.

摘要翻译： 个人计算机（PC）卡插入方法和装置使用位于连接器两端的连接器接地端子和引脚的子集，用于检测卡插入的开始。 主机PC卡插槽连接器具有用于将接地端子子集保持在高逻辑电平（VCC）的上拉电阻。 此外，引脚的子集比信号引脚长，使得当PC卡的插入开始时，引脚子集中的一个或多个的接地表示PC卡插入已经开始，允许主机系统采取 必要的预防措施，以确保有序地接受卡而没有任何不期望的系统可能会导致的影响。 此外，在插入完成时提供用于使用连接器端子子集作为附加接地连接的逻辑网络。

公开(公告)号：US20180268855A1

公开(公告)日：2018-09-20

申请号：US15987037

申请日：2018-05-23

申请人： Jasmin Ajanovic

发明人： Jasmin Ajanovic

IPC分类号： G11B7/09 ,  G11B7/013 ,  G11B7/005 ,  G11B7/007 ,  G11B7/1362 ,  G11B7/085 ,  G11B7/127

CPC分类号： G11B7/09 ,  G11B7/005 ,  G11B7/007 ,  G11B7/013 ,  G11B7/085 ,  G11B7/127 ,  G11B7/1362

摘要： Systems and methods for long-term non-volatile non-rotating optical storage of digital information rely on storage elements that include optical storage media, an access subsystem configured to access bits of information from one of the storage elements, and a support structure configured to support multiple storage elements. A laser used to retrieve and/or record bits of digital information may be moved along two orthogonal dimensions while the storage element is non-rotating.

公开(公告)号：US08793404B2

公开(公告)日：2014-07-29

申请号：US13493606

申请日：2012-06-11

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20140115219A1

公开(公告)日：2014-04-24

申请号：US14144309

申请日：2013-12-30

申请人： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

发明人： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC分类号： G06F13/40

CPC分类号： G06F13/4068 ,  A47K7/028 ,  G06F13/4273 ,  G06F2213/0026

摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US08555101B2

公开(公告)日：2013-10-08

申请号：US13046345

申请日：2011-03-11

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F13/00 ,  G06F13/42 ,  G06F13/14 ,  H04M1/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

公开(公告)号：US20130254451A1

公开(公告)日：2013-09-26

申请号：US13730024

申请日：2012-12-28

申请人： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

发明人： Jasmin Ajanovic ,  David Harriman ,  Blaise Fanning ,  David Lee

IPC分类号： G06F13/42

CPC分类号： H04L47/10 ,  G06F5/06 ,  G06F13/124 ,  G06F13/385 ,  G06F13/4059 ,  G06F13/42 ,  G06F13/4221 ,  G06F13/4252 ,  G06F13/4265 ,  G06F13/4269 ,  G06F13/4282 ,  H04L47/30

摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.

公开(公告)号：US08447888B2

公开(公告)日：2013-05-21

申请号：US13316349

申请日：2011-12-09

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Abraham Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US08412855B2

公开(公告)日：2013-04-02

申请号：US12689899

申请日：2010-01-19

申请人： Kenneth C. Creta ,  Aaron T. Spink ,  Lance E. Hacking ,  Sridhar Muthrasanallur ,  Jasmin Ajanovic

发明人： Kenneth C. Creta ,  Aaron T. Spink ,  Lance E. Hacking ,  Sridhar Muthrasanallur ,  Jasmin Ajanovic

IPC分类号： G06F13/00

CPC分类号： G06F13/4027

摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.

摘要翻译： 处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。 与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

公开(公告)号：US08161243B1

公开(公告)日：2012-04-17

申请号：US11906176

申请日：2007-09-28

申请人： Mahesh Wagh ,  Jasmin Ajanovic

发明人： Mahesh Wagh ,  Jasmin Ajanovic

IPC分类号： G06F12/10 ,  G06F12/12

CPC分类号： G06F12/08 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/152

摘要： Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by an endpoint device may be utilized to update information stored in an I/O cache. Such information may be utilized for implementation of a more efficient replacement policy in an embodiment. Other embodiments are also disclosed.

摘要翻译： 描述了在虚拟化环境中改进地址转换缓存和/或输入/输出（I / O）缓存性能的方法和装置。 在一个实施例中，由端点设备提供的提示可用于更新存储在I / O高速缓存中的信息。 这样的信息可以用于在实施例中实现更有效的替换策略。 还公开了其他实施例。

公开(公告)号：US20120036293A1

公开(公告)日：2012-02-09

申请号：US13198559

申请日：2011-08-04

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David Harriman ,  Mark Rosenbluth ,  Ajay Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert Blankenship ,  Ohad Falik ,  Avi (Abraham) Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F3/00

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.