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公开(公告)号：US08472004B2
公开(公告)日：2013-06-25
申请号：US11335251
申请日：2006-01-18
IPC分类号： G03B27/52
CPC分类号： G03F7/70358 , G03F7/70341
摘要： An immersion photolithography system includes a lens system positioned to focus radiation emitted from the radiation source onto a workpiece or wafer on a stage. A liquid supply system provides liquid between the lens of the lens system closest to the wafer. A seal element encloses a volume of liquid which keeps the lower or wetted surface of the lens wet. The seal element may be located at a lens parking location adjacent to the stage. The system provides an improved way for keeping the lens wet between exposure processing.
摘要翻译： 浸没式光刻系统包括透镜系统，其被定位成将从辐射源发射的辐射聚焦到台上的工件或晶片上。 液体供应系统在最接近晶片的透镜系统的透镜之间提供液体。 密封元件包围一定体积的液体，其保持透镜的下部或底部表面湿润。 密封元件可以位于与舞台相邻的镜头停车位置。 该系统提供了在曝光处理之间保持透镜湿润的改进方式。
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62.发明授权公开(公告)号：US08409933B2
公开(公告)日：2013-04-02
申请号：US13302231
申请日：2011-11-22
IPC分类号： H01L21/82 , H01L21/338 , H01L21/326
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
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63.发明授权Two-terminal nanotube devices including a nanotube bridge and methods of making same 有权包括纳米管桥的两端纳米管装置及其制造方法公开(公告)号：US08134220B2
公开(公告)日：2012-03-13
申请号：US12139910
申请日：2008-06-16
CPC分类号： H01L51/0591 , B82Y10/00 , G11C13/025 , H01L51/0048 , Y10S977/943
摘要： Nanotube switching devices having nanotube bridges are disclosed. Two-terminal nanotube switches include conductive terminals extending up from a substrate and defining a void in the substrate. Nantoube articles are suspended over the void or form a bottom surface of a void. The nanotube articles are arranged to permanently contact at least a portion of the conductive terminals. An electrical stimulus circuit in communication with the conductive terminals is used to generate and apply selected waveforms to induce a change in resistance of the device between relatively high and low resistance values. Relatively high and relatively low resistance values correspond to states of the device. A single conductive terminal and a interconnect line may be used. The nanotube article may comprise a patterned region of nanotube fabric, having an active region with a relatively high or relatively low resistance value. Methods of making each device are disclosed.
摘要翻译： 公开了具有纳米管桥的纳米管开关器件。 两端纳米管开关包括从衬底向上延伸并且在衬底中限定空隙的导电端子。 纳米管制品悬浮在空隙上或形成空隙的底部表面。 纳米管制品布置成永久地接触导电端子的至少一部分。 使用与导电端子连通的电刺激电路来产生并施加所选择的波形以引起器件在较高和较低电阻值之间的电阻变化。 相对较高且相对较低的电阻值对应于器件的状态。 可以使用单个导电端子和互连线。 纳米管制品可以包括具有相对较高或相对低的电阻值的有源区的纳米管织物的图案化区域。 公开了制造每个装置的方法。
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公开(公告)号：US07858486B2
公开(公告)日：2010-12-28
申请号：US12420613
申请日：2009-04-08
IPC分类号： H01L21/8242
CPC分类号： H01L27/0805 , H01L27/101 , H01L27/10808 , H01L27/10852 , H01L28/90 , H01L28/91
摘要： The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated.
摘要翻译： 本发明包括方法和集成电路。 支柱从单个电容器存储节点位置的第一材料的开口向外突出。 绝缘材料在突出柱的侧壁周围横向沉积在第一材料上，并且被各向异性蚀刻有效地暴露下面的第一材料并且留下横向于突出支柱的侧壁横向接收的电绝缘材料。 开口形成在支柱的第二材料内。 支柱通过第二材料中的开口从衬底上蚀刻出来，并且单独的电容器电极形成在与存储节点位置电连接的开口内。 单独的电容器电极具有各向异性蚀刻的绝缘材料，其横向地围绕其外侧壁接收。 各个电容器电极被并入到多个电容器中。 考虑其他实现和方面。
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公开(公告)号：US20100290268A1
公开(公告)日：2010-11-18
申请号：US12844045
申请日：2010-07-27
IPC分类号： G11C11/24
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10823
摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with adjacent memory cells and the plurality of access transistor selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in the substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
摘要翻译： 存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。 数字线与相邻的存储器单元耦合，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。 形成存储单元的方法包括在衬底中形成掩埋的数字线，并且在与衬底数字线紧邻的衬底中形成垂直柱。 双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。
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公开(公告)号：US07825451B2
公开(公告)日：2010-11-02
申请号：US11787079
申请日：2007-04-12
IPC分类号： H01L29/76
CPC分类号： H01L27/0805 , H01L27/101 , H01L27/10808 , H01L27/10852 , H01L28/90 , H01L28/91
摘要： The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node locations. Insulative material is deposited over the first material laterally about sidewalls of the projecting pillars, and is anisotropically etched effective to expose underlying first material and leave electrically insulative material received laterally about the sidewalls of the projecting pillars. Openings are formed within a second material to the pillars. The pillars are etched from the substrate through the openings in the second material, and individual capacitor electrodes are formed within the openings in electrical connection with the storage node locations. The individual capacitor electrodes have the anisotropically etched insulative material received laterally about their outer sidewalls. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other implementations and aspects are contemplated.
摘要翻译： 本发明包括方法和集成电路。 支柱从单个电容器存储节点位置的第一材料的开口向外突出。 绝缘材料在突出柱的侧壁周围横向沉积在第一材料上，并且被各向异性蚀刻有效地暴露下面的第一材料并且留下横向于突出支柱的侧壁横向接收的电绝缘材料。 开口形成在支柱的第二材料内。 支柱通过第二材料中的开口从衬底上蚀刻出来，并且单独的电容器电极形成在与存储节点位置电连接的开口内。 单独的电容器电极具有各向异性蚀刻的绝缘材料，其横向地围绕其外侧壁接收。 各个电容器电极被并入到多个电容器中。 考虑其他实现和方面。
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公开(公告)号：US20100270641A1
公开(公告)日：2010-10-28
申请号：US12832840
申请日：2010-07-08
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.
摘要翻译： 本发明包括在多个导电连接件上并与之电接触的包含导电板的半导体熔丝装置。 每个链接件相对于其它连接件与导电板接触作为一个单独的区域，并且链接件与导电板接触的区域是熔丝。 本发明还包括形成半导体熔丝装置的方法。
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公开(公告)号：US07767525B2
公开(公告)日：2010-08-03
申请号：US11486524
申请日：2006-07-13
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.
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公开(公告)号：US07737022B2
公开(公告)日：2010-06-15
申请号：US12401996
申请日：2009-03-11
IPC分类号： H01L21/4763
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76831 , H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.
摘要翻译： 本公开包括各种方法，电路，设备和系统实施例。 一种这样的方法实施例包括在绝缘体堆叠材料中形成沟槽，其具有位于多个栅极中的两个之间的沟槽的一部分，并且将间隔物材料沉积到沟槽的至少一个侧表面。 该方法还包括将导电材料沉积到沟槽中并将盖材料沉积到沟槽中。
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公开(公告)号：US07687358B2
公开(公告)日：2010-03-30
申请号：US11171873
申请日：2005-06-30
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。
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