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168 条记录 (耗时 0.026 秒)

    Methods of forming a gated device
    2.
    发明授权
    Methods of forming a gated device 有权
    形成门控装置的方法

    公开(公告)号：US07687358B2

    公开(公告)日：2010-03-30

    申请号：US11171873

    申请日：2005-06-30

    申请人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

    发明人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

    Gated field effect devices
    3.
    发明授权
    Gated field effect devices 失效
    门控场效应器件

    公开(公告)号：US07442977B2

    公开(公告)日：2008-10-28

    申请号：US11253461

    申请日：2005-10-19

    申请人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

    发明人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

    IPC分类号： H01L27/108

    CPC分类号： H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

    Methods of forming vertical transistor structures
    4.
    发明授权
    Methods of forming vertical transistor structures 有权
    形成垂直晶体管结构的方法

    公开(公告)号：US07846798B2

    公开(公告)日：2010-12-07

    申请号：US11486512

    申请日：2006-07-13

    申请人： H. Montgomery Manning ,  Kunal R. Parekh ,  Cem Basceri ,  Gurtej S. Sandhu

    发明人： H. Montgomery Manning ,  Kunal R. Parekh ,  Cem Basceri ,  Gurtej S. Sandhu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66787 ,  H01L27/10808 ,  H01L27/10876

    摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

    摘要翻译： 本发明包括这样的方法，其中使用成角度的注入来使源极/漏极区域注入与垂直晶体管结构的天线的顶部边缘自对准。 本发明还包括其中使用成角度的植入物以在垂直晶体管结构的栅极下注入掺杂剂的方法。 根据本发明的方法形成的垂直晶体管结构可以结合到各种类型的集成电路中，包括例如DRAM阵列。

    Gated field effect device comprising gate dielectric having different K regions
    5.
    发明授权
    Gated field effect device comprising gate dielectric having different K regions 有权
    门极场效应器件包括具有不同K区域的栅极电介质

    公开(公告)号：US07161203B2

    公开(公告)日：2007-01-09

    申请号：US10861744

    申请日：2004-06-04

    申请人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

    发明人： Cem Basceri ,  H. Montgomery Manning ,  Gurtej S. Sandhu ,  Kunal R. Parekh

    IPC分类号： H01L27/108

    CPC分类号： H01L29/4983 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括门控场效应器件，以及形成门控场效应器件的方法。 在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。 在源极/漏极区域之间的沟道区域附近接收栅极。 栅极在源极/漏极区之间具有栅极宽度。 栅极电介质被接收在沟道区域和栅极之间。 栅极电介质沿着栅极的宽度具有至少两个不同的区域。 不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。 考虑了其他方面和实现。

    Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array
    6.
    发明授权
    Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive oxide memory array 有权
    形成非易失性电阻氧化物存储单元的方法和形成非易失性电阻氧化物存储器阵列的方法

    公开(公告)号：US09343665B2

    公开(公告)日：2016-05-17

    申请号：US12166604

    申请日：2008-07-02

    申请人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

    发明人： Nishant Sinha ,  John Smythe ,  Bhaskar Srinivasan ,  Gurtej S. Sandhu ,  Joseph Neil Greeley ,  Kunal R. Parekh

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1683 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

    摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 含金属氧化物的材料形成在第一导电电极上。 蚀刻停止材料沉积在包含金属氧化物的材料上。 导电材料沉积在蚀刻停止材料上。 包含所接收的导电材料的存储单元的第二导电电极形成在蚀刻停止材料上。 这样包括通过导电材料蚀刻以相对于蚀刻停止材料停止并且形成非易失性电阻氧化物存储单元，以包括具有包含金属氧化物的材料和其间的蚀刻停止材料的第一和第二导电电极。 考虑其他实现。