公开(公告)号：US20190123191A1

公开(公告)日：2019-04-25

申请号：US15828898

申请日：2017-12-01

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： Dae Hwan Chun

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238

Abstract: A semiconductor device includes: an n+ type of silicon carbide substrate, an n− type of layer, first trenches, a p type of region, a p+ type of region, an n+ type of region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells, wherein one of the plurality of unit cells may include a contact portion at which the source electrode and the p+ type of region contact each other, an outer portion disposed at upper and lower portions of the contact portion in a plan view, and a connection portion connecting the contact portion to the outer portion, a width between the first trenches horizontally adjacent in the plan view in the contact portion is equal to a width between the first trenches horizontally adjacent in the plan view in the outer portion, and a width between the first trenches horizontally adjacent in the plan view in the connection portion is less than a width between the first trenches horizontally adjacent in the plan view in the contact portion.

公开(公告)号：US10121863B2

公开(公告)日：2018-11-06

申请号：US15631993

申请日：2017-06-23

Applicant: Hyundai Motor Company ,  Kia Motors Corporation

Inventor： NackYong Joo ,  Youngkyun Jung ,  Junghee Park ,  JongSeok Lee ,  Dae Hwan Chun

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device may include an n− type layer sequentially disposed at a first surface of an n+ type silicon carbide substrate; a p type region disposed in the n− type layer; an auxiliary n+ type region disposed on the p type region or in the p type region; an n+ type region disposed in the p type region; an auxiliary electrode disposed on the auxiliary n+ type region and the p type region; a gate electrode separated from the auxiliary electrode and disposed on the n− type layer; a source electrode separated from the auxiliary electrode and the gate electrode; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the auxiliary n+ type region and the n+ type region are separated from each other, and the source electrode is in contact with the n+ type region.

公开(公告)号：US10115816B2

公开(公告)日：2018-10-30

申请号：US15187485

申请日：2016-06-20

Applicant: Hyundai Motor Company

Inventor： Dae Hwan Chun ,  Youngkyun Jung ,  Nackyong Joo ,  Junghee Park ,  Jong Seok Lee

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04

Abstract: A semiconductor device is provided. The device includes an n− type layer with a trench disposed in a first surface of an n+ type silicon carbide substrate. An n+ type region and a first p type region are disposed at the n− type layer and at a lateral surface of the trench. A plurality of second p type regions are disposed at the n− type layer and spaced apart from the first p type region. A gate electrode includes a first and a plurality of second gate electrodes disposed at the trench and extending from the first gate electrode, respectively. A source electrode is disposed on and insulated from the gate electrode. A drain electrode is disposed on a second surface of the n+ type silicon carbide substrate. The source electrode contacts the plurality of second p type regions spaced apart with the n− type layer disposed therein.

公开(公告)号：US09755020B2

公开(公告)日：2017-09-05

申请号：US15342363

申请日：2016-11-03

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Dae Hwan Chun ,  Youngkyun Jung ,  Nack Yong Joo ,  Junghee Park ,  Jong Seok Lee

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/78 ,  H01L29/861

CPC classification number: H01L29/0847 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/1608 ,  H01L29/78 ,  H01L29/7828

Abstract: A semiconductor device includes a first n− type layer and a second n− type layer that are sequentially disposed on a first surface of an n+ type silicon carbide substrate; a first trench and a second trench that are disposed at the second n− type layer and are spaced apart from each other; a p type region surrounding a lateral surface and a lower surface of the first trench; an n+ type region disposed on the p type region and the second n− type layer; a gate insulating layer disposed in the second trench; a gate electrode disposed on the gate insulating layer; an oxide layer disposed on the gate electrode; a source electrode disposed on the oxide layer and the n+ type region disposed in the first trench; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate.

公开(公告)号：US09236500B2

公开(公告)日：2016-01-12

申请号：US14143735

申请日：2013-12-30

Applicant: Hyundai Motor Company

Inventor： Jong Seok Lee ,  Kyoung-Kook Hong ,  Dae Hwan Chun ,  Youngkyun Jung

IPC: H01L29/06 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66143

Abstract: A Schottky barrier diode and a method of manufacturing the Schottky barrier diode are provided. The diode includes an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and having an upper surface, a lower surface, and an inclined surface that connects the upper surface and the lower surface. A p region is disposed on the inclined surface of the n− type epitaxial layer and a Schottky electrode is disposed on the upper surface of the n− type epitaxial layer and the p region. In addition, an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate.

Abstract translation: 提供肖特基势垒二极管和制造肖特基势垒二极管的方法。 二极管包括n型外延层，其设置在n +型碳化硅衬底的第一表面上，并具有上表面，下表面和连接上表面和下表面的倾斜表面。 p区设置在n型外延层的倾斜面上，肖特基电极设置在n型外延层和p区的上表面上。 此外，欧姆电极设置在n +型碳化硅衬底的第二表面上。

公开(公告)号：US09159847B2

公开(公告)日：2015-10-13

申请号：US14098359

申请日：2013-12-05

Applicant: Hyundai Motor Company

Inventor： Jong Seok Lee ,  Kyoung-Kook Hong ,  Dae Hwan Chun ,  Youngkyun Jung

IPC: H01L31/0312 ,  H01L29/872 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/872 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0804 ,  H01L29/1608 ,  H01L29/6606

Abstract: A schottky barrier diode includes: an n− type epitaxial layer that is disposed at a first surface of an n+ type silicon carbide substrate; a plurality of n type pillar areas that are disposed at the inside of the n− type epitaxial layer and that are disposed at a first portion of the first surface of the n+ type silicon carbide substrate; a p type area that is disposed at the inside of the n− type epitaxial layer and that is extended in a direction perpendicular to the n type pillar areas; a plurality of p+ areas in which the n− type epitaxial layer is disposed at a surface thereof and that are separated from the n type pillar areas and the p type area; a schottky electrode that is disposed on the n− type epitaxial layer and the p+ areas; and an ohmic electrode that is disposed at a second surface of the n+ type silicon carbide substrate.

Abstract translation: 肖特基势垒二极管包括：n型外延层，其设置在n +型碳化硅衬底的第一表面; 多个n型支柱区域，其设置在n型外延层的内部，并且设置在n +型碳化硅衬底的第一表面的第一部分; p型区域，其设置在所述n型外延层的内部，并且在垂直于所述n型支柱区域的方向上延伸; 多个p +区域，其中n型外延层设置在其表面并且与n型支柱区域和p型区域分离; 设置在n型外延层和p +区域上的肖特基电极; 以及设置在n +型碳化硅衬底的第二表面的欧姆电极。

公开(公告)号：US09142644B2

公开(公告)日：2015-09-22

申请号：US14079222

申请日：2013-11-13

Applicant: Hyundai Motor Company

Inventor： Jong Seok Lee ,  Kyoung-Kook Hong ,  Dae Hwan Chun ,  Youngkyun Jung

IPC: H01L29/772 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L29/0688 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7834

Abstract: The present inventive concept has been made in an effort to increase the width of a channel in a silicon carbide MOSFET using a trench gate.According to the exemplary embodiment of the present inventive concept, the width of a channel can be increased, compared with the conventional art, by forming a plurality of protrusions extending to the p type epitaxial layer on both sides of the trench.

Abstract translation: 本发明构思是为了增加使用沟槽栅极的碳化硅MOSFET中的沟道的宽度。 根据本发明构思的示例性实施例，与传统技术相比，可以通过在沟槽的两侧形成延伸到p型外延层的多个突起来增加通道的宽度。

公开(公告)号：US20140187004A1

公开(公告)日：2014-07-03

申请号：US13830260

申请日：2013-03-14

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Dae Hwan Chun ,  Jong Seok Lee ,  Kyoung-Kook Hong ,  Youngkyun Jung

IPC: H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: Disclosed is a method for fabricating a semiconductor device including: sequentially forming a first insulating film and a first barrier layer on a first surface of a substrate; etching the first barrier layer to form a first barrier layer pattern; etching the first insulating film to form a first insulating film pattern; removing the first barrier layer pattern and forming a first type epitaxial layer on an exposed first portion of the substrate; forming a second insulating film and a second barrier layer on the first type epitaxial layer and the first insulating film pattern; etching the second barrier layer to form a second barrier layer pattern; etching the second insulating film to form a second insulating film pattern, and etching the first insulating film pattern; and forming a second type epitaxial layer on an exposed second portion of the first surface of the n substrate.

Abstract translation: 公开了一种制造半导体器件的方法，包括：在衬底的第一表面上依次形成第一绝缘膜和第一阻挡层; 蚀刻第一阻挡层以形成第一阻挡层图案; 蚀刻第一绝缘膜以形成第一绝缘膜图案; 去除所述第一阻挡层图案并在所述基板的暴露的第一部分上形成第一类型的外延层; 在所述第一型外延层和所述第一绝缘膜图案上形成第二绝缘膜和第二阻挡层; 蚀刻第二阻挡层以形成第二阻挡层图案; 蚀刻第二绝缘膜以形成第二绝缘膜图案，并蚀刻第一绝缘膜图案; 以及在所述n基板的所述第一表面的暴露的第二部分上形成第二类型的外延层。

公开(公告)号：US20140117379A1

公开(公告)日：2014-05-01

申请号：US13729641

申请日：2012-12-28

Applicant: HYUNDAI MOTOR COMPANY

Inventor： Youngkyun JUNG ,  Kyoung-Kook Hong ,  Jong Seok Lee ,  Dae Hwan Chun

IPC: H01L29/16 ,  H01L21/36

CPC classification number: H01L29/1608 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/42356 ,  H01L29/7827

Abstract: A method of manufacturing a semiconductor device includes sequentially forming an n− type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate, and forming a trench through the first n+ region and the p type epitaxial layer, wherein the forming of the trench includes forming a photosensitive layer pattern on the first n+ region, etching the first n+ region and the p type epitaxial layer by using the photosensitive layer pattern as a mask, forming a buffer layer by using amorphous carbon on the first n+ region after the photosensitive layer pattern is removed, forming a buffer layer pattern by etching the buffer layer, etching using the buffer layer pattern as the mask, isotropically etching to form a second portion of the trench, and removing the buffer layer pattern.

Abstract translation: 一种制造半导体器件的方法包括：在n +型碳化硅衬底的第一表面上依次形成n-型外延层，ap型外延层和第一n +区，以及通过第一n +区形成沟槽， p型外延层，其中所述沟槽的形成包括在所述第一n +区上形成感光层图案，通过使用所述感光层图案作为掩模蚀刻所述第一n +区和所述p型外延层，通过使用 除去感光层图案后的第一n +区域上的无定形碳，通过蚀刻缓冲层形成缓冲层图案，使用缓冲层图案进行蚀刻作为掩模，各向同性蚀刻以形成沟槽的第二部分， 缓冲层图案。