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    Semiconductor memory cells with shared p-type well
    64.
    发明授权
    Semiconductor memory cells with shared p-type well 有权
    具有共享p型的半导体存储器单元

    公开(公告)号：US07710764B2

    公开(公告)日：2010-05-04

    申请号：US11783123

    申请日：2007-04-06

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C11/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit includes: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    摘要翻译： 一种具有存储器冗余电路的半导体集成电路，用于解决由使用ECC电路进行纠错引起的增加的面积，功耗和访问时间的问题。 电路包括：多个存储垫; 平行于字线的本地总线，其传送读取数据并从存储器单元写入数据; 与数据线并行的写入全局总线，其从输入焊盘IO传送写入数据; 用于读取数据线的全局总线，其将读取的数据传送到输出焊盘IO; 以及位于全局总线和本地总线的交叉点处的至少一个纠错电路。 读取和写入可以在单个周期中完成，并且在写入操作期间，写入与先前读取的数据不同的数据。 通过这种配置，可以避免面积和功耗的增加，并且可以校正诸如软错误的错误。

    SRAM memory semiconductor integrated circuit device
    66.
    发明授权
    SRAM memory semiconductor integrated circuit device 有权
    SRAM存储器半导体集成电路器件

    公开(公告)号：US07408231B2

    公开(公告)日：2008-08-05

    申请号：US11188735

    申请日：2005-07-26

    申请人： Koichiro Ishibashi ,  Kenichi Osada

    发明人： Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： H01L29/78

    CPC分类号： G11C11/404 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/104 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

    摘要翻译： 在集成电路器件中，根据电路的特性，存在各种最佳栅极长度，栅极氧化膜的厚度和阈值电压。 在其中电路集成在同一基板上的半导体集成电路器件中，制造过程复杂以便将电路设置为最佳值。 结果，伴随着产量的恶化和制造日数的增加，制造成本增加。 为了解决这些问题，根据本发明，在逻辑电路中使用高阈值和低阈值的晶体管，存储单元使用具有相同高阈值电压的晶体管和低阈值电压晶体管，以及输入/输出电路 使用在通道中具有相同高阈值电压和相同浓度的晶体管，以及较厚的栅极氧化物膜。