Abstract:
An electropolishing apparatus for polishing a metal layer formed on a wafer (31) includes an electrolyte (34), a polishing receptacle (100), a wafer chuck (29), a fluid inlet (5, 7, 9), and at least one cathode (1, 2, 3). The wafer chuck (29) holds and positions the wafer (31) within the polishing receptacle (100). The electrolyte (34) is delivered through the fluid inlet (5, 7, 9) into the polishing receptacle (100). The cathode (1, 2, 3) then applies an electropolishing current to the electrolyte to electropolish the wafer (31). In accordance with one aspect of the present invention, discrete portions of the wafer (31) can be electropolished to enhance the uniformity of the electropolished wafer.
Abstract:
A storm resistant device for a window that has a window frame enclosing at least one sash slidingly and pivotally mounted therein. The sash has side rails and the frame has vertical jambs that engage the side rails of the sash to raise and lower and pivot the sash. The storm resistant device comprises a first elongated bracket having a substantially Z-shaped cross section with two end segments and a middle segment connecting the two end segments. The middle segment is connectable to the side rails of the sashes with one of the end segments extending outward from the sash toward an adjacent jamb. There is a second elongated bracket having a substantially L-shaped cross section with two legs, one leg of the bracket adapted to be mounted to the jamb with a second leg of the L extending toward an adjacent side rail of the sash. The first and second brackets are mounted to the frame and sash, respectively, so that when the sash is closed, the one end segment of the first bracket interlocks with the second leg of the second bracket and prevents the sash from pivoting when pressure is applied to the sash.
Abstract:
Fluorinated chemical precursors, methods of manufacture, polymer thin filmswith low dielectric constants, and integrated circuits comprising primarily of sp2C—F and some hyperconjugated sp3C—F bonds are disclosed in this invention. Precursors are disclosed for creating fluorinated silanes and siloxanes, and fluorinated hydrocarbon polymers. Thermal transport polymerization (TP), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), high density PECVD (HDPCVD), photon assisted CVD (PACVD), and plasma-photon assisted (PPE) CVD and PPETP of these chemicals provides thin films with low dielectric constants and high thermal stabilities for use in the manufacture of integrated circuits.
Abstract:
A wafer chuck for holding a wafer during electropolishing and/or electroplating of the wafer includes a top section, a bottom section, and a spring member. In accordance with one aspect of the present invention, the top section and the bottom section are configured to receive the wafer for processing. The spring member is disposed on the bottom section and configured to apply an electric charge to the wafer. In accordance with another aspect of the present invention, the spring member contacts a portion of the outer perimeter of the wafer. In one alternative configuration of the present invention, the wafer chuck further includes a seal member to seal the spring member from the electrolyte solution used in the electropolishing and/or electroplating process.
Abstract:
The described deposition systems are designed to accommodate new precursors and chemical processes used for transport polymerization and chemical vapor deposition. The systems consist primarily of a reactor, a liquid injector or gas mass flow controller, a cracker and a deposition chamber under sub-atmospheres pressure. The cracker utilizes one or more types of energy, including heat, photons, and plasmas. This invention is especially useful for preparing F-PPX (fluorinated poly(para-xylylenes) and other fluorinated polymer thin films for intermetal dielectric (IMD) and interlevel dielectric (ILD) applications in the manufacture of integrated circuits with features
Abstract:
A method and apparatus for producing x-ray and/or extreme ultraviolet (EUV) is described. A liquid edge 2 is electrically connected to a cathode 8 via a high voltage pulse power supply 10. Liquid edge 2 is set to be parallel to cathode 8. When high voltage pulse power supply 10 is turned on, a vacuum discharge will occur in a space between liquid edge 2 and cathode 8. The plasma will be confined into a high density and high temperature thin plasma column 4 in a space near liquid edge 2 by strong magnetic field induced by the huge discharge current. A population inversion in the confined plasma column will lead to a amplified simultaneous emission of x-ray and/or EUV 6 along the axis of plasma column 4. Moreover, a large power x-ray and/or EUV laser can be built by using multi-liquid edge-shape anodes placed in a straight line and operated in a traveling-wave mode.
Abstract:
A method and apparatus are provided for generating x-ray photon radiation. A liquid cone anode and an extraction electrode spaced therefrom are disposed in a vacuum chamber. The liquid cone anode comprises a liquid material, a reservoir for holding the liquid material having an opening for passage of the liquid material, and a liquid material feeding and cone forming mechanism operatively associated with the reservoir for feeding liquid material through the opening in the reservoir and for forming a liquid cone from the liquid material A power supply is connected to the liquid cone anode and the extraction electrode for creating an electric field therebetween of sufficient strength to cause particles to be extracted from the liquid cone anode to form a plasma ball in the space between the liquid cone anode and the extraction electrode which emits x-ray photon radiation.
Abstract:
Identifying data for placement in a storage system having a plurality of storage classes includes subdividing the data into portions, for each of the portions, independently determining at least one score for a particular portion based on a metric corresponding to access of the particular portion, where the at least one score for the particular portion is independent of scores for other ones of the portions, and identifying sub-portions of data for placement in a particular storage class based on the at least one score of a portion of data corresponding to the sub-portions. The at least one score may be based on short term access statistics and long term access statistics. The access statistics may include read misses, writes, and prefetches.
Abstract:
When migrating data, a first message is received at a target data storage system from a source data storage system. The target data storage system includes a data storage optimizer that performs automated data movement optimizations. The first message requests a reservation of a first amount of storage on a first storage tier for performing a data migration to migrate data from the source to the target data storage system. A first capacity limit of the first storage tier is reduced by the first amount thereby representing the reservation of the first amount of storage for performing the data migration. If the first storage tier does not include an amount of available storage of at least the first amount, processing is performed to increase the amount of available storage of the first storage tier.
Abstract:
The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.