公开(公告)号：US20170207312A1

公开(公告)日：2017-07-20

申请号：US15327641

申请日：2014-08-19

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/423 ,  H01L23/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/535

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/66 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US11251201B2

公开(公告)日：2022-02-15

申请号：US17072850

申请日：2020-10-16

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US10892192B2

公开(公告)日：2021-01-12

申请号：US15930700

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Roman W. Olac-Vaw ,  Walid M. Hafez ,  Chia-Hong Jan ,  Pei-Chi Liu

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L21/28 ,  H01L23/528 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US10707346B2

公开(公告)日：2020-07-07

申请号：US15754151

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation. The structure and forming techniques are compatible with both planar and non-planar transistor architectures.

公开(公告)号：US10692888B2

公开(公告)日：2020-06-23

申请号：US15946666

申请日：2018-04-05

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US10559688B2

公开(公告)日：2020-02-11

申请号：US16081215

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Chen-Guan Lee ,  Walid M. Hafez ,  Joodong Park ,  Chia-Hong Jan ,  Hsu-Yu Chang

IPC: H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.

公开(公告)号：US10431661B2

公开(公告)日：2019-10-01

申请号：US15778304

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Jui-Yen Lin ,  Chia-Hong Jan

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L21/3213 ,  H01L21/764 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08

Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ⊥-shape, L-shape, or ┘-shape, for example.

公开(公告)号：US10355081B2

公开(公告)日：2019-07-16

申请号：US15885468

申请日：2018-01-31

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan

IPC: H01L29/80 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/808 ,  H01L29/8605 ,  H01L27/098

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.

公开(公告)号：US10312367B2

公开(公告)日：2019-06-04

申请号：US15301282

申请日：2014-06-20

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Nidhi Nidhi ,  Chia-Hong Jan ,  Ting Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/092

Abstract: High voltage transistors spanning multiple non-planar semiconductor bodies, such as fins or nanowires, are monolithically integrated with non-planar transistors utilizing an individual non-planar semiconductor body. The non-planar FETs may be utilized for low voltage CMOS logic circuitry within an IC, while high voltage transistors may be utilized for high voltage circuitry within the IC. A gate stack may be disposed over a high voltage channel region separating a pair of fins with each of the fins serving as part of a source/drain for the high voltage device. The high voltage channel region may be a planar length of substrate recessed relative to the fins. A high voltage gate stack may use an isolation dielectric that surrounds the fins as a thick gate dielectric. A high voltage transistor may include a pair of doped wells formed into the substrate that are separated by the high voltage gate stack with one or more fin encompassed within each well.

公开(公告)号：US10263112B2

公开(公告)日：2019-04-16

申请号：US15353631

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Curtis Tsai ,  Jeng-Ya D. Yeh ,  Joodong Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

Abstract: Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate, the semiconductor fin having a recessed portion and an uppermost portion. A source region is disposed in the recessed portion of the semiconductor fin. A drain region is disposed in the uppermost portion of the semiconductor fin. A gate electrode is disposed over the uppermost portion of the semiconductor fin, between the source and drain regions.