公开(公告)号：US20220418145A1

公开(公告)日：2022-12-29

申请号：US17898323

申请日：2022-08-29

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  George VERGIS

IPC: H05K7/14

Abstract: A server memory device provides highspeed storage to a computer system. The server memory device has a connector that can make electrical coupling with the computer system. The server memory device includes two memory modules, each with one or more memory chips. Each memory module is coupled and bonded with an interposer. Each interposer is coupled and bonded with the server memory device connector. The connector and interposers provide a high-density interconnect that connects two memory modules to a computer system. The server memory device has a form factor that uses a single unit (1U) of a server rack, doubling the memory capacity provided to the computer system through a single unit (1U) equipment rack.

公开(公告)号：US20220418090A1

公开(公告)日：2022-12-29

申请号：US17897043

申请日：2022-08-26

Applicant: Intel Corporation

Inventor： Landon HANKS ,  Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H05K1/02 ,  H01R12/72 ,  H01R12/73 ,  H05K1/11 ,  H05K1/18 ,  H05K3/10

Abstract: Examples described herein relate to a system that includes: a circuit board comprising a plurality of layers, first and second conductive connections, first and second trace portions, first, second, and third routings, and a via wherein: the first conductive connection is coupled to the first trace portion, the second conductive connection is coupled to the second trace portion, the first routing is formed in a first layer of the plurality of layers, the second routing is formed in a second layer of the plurality of layers, the third routing is formed in the first layer of the plurality of layers, a portion of the first routing overlaps with a portion of the second routing to provide a capacitive region, and the via conductively couples a portion of the second routing overlaps with a portion of the third routing.

公开(公告)号：US20220358072A1

公开(公告)日：2022-11-10

申请号：US17874117

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： George VERGIS ,  Xiang LI ,  Jun LIAO ,  Anthony M. CONSTANTINE ,  Min Suet LIM ,  Tongyan ZHAI ,  Konika GANGULY

IPC: G06F13/40 ,  G06F12/06

Abstract: A memory module adapter card can adapt multiple compression-attached memory modules (CAMMs) to a dual inline memory module (DIMM) connector. Multiplexer circuitry on the adapter card enables multiplexing data amongst the memory modules attached to the adapter card during a same burst access sequence.

公开(公告)号：US20220304142A1

公开(公告)日：2022-09-22

申请号：US17831774

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Xiang LI ,  Landon HANKS ,  George VERGIS ,  James A. McCALL

IPC: H05K1/02 ,  H05K3/46

Abstract: Examples described herein relate to a system that includes: a circuit board comprising a plurality of layers and at least one conductive connection. In some examples, the at least one conductive connection is connected to a layer of the plurality of layers. In some examples, at least one layer of the plurality of layers comprises a conductive material. In some examples, the at least two layers of the plurality of layers comprise conductive material that extend in an axis towards the at least one conductive connection but do not overlap with the at least one layer of the plurality of layers comprising the conductive material.

公开(公告)号：US20210312953A1

公开(公告)日：2021-10-07

申请号：US17351556

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS

IPC: G11C5/02 ,  G06F1/18 ,  H01R13/11 ,  G11C5/06 ,  H05K7/14

Abstract: An apparatus is described. The apparatus includes a DIMM socket having a seating floor that is to meet both longer length contacts and shorter length contacts of a DIMM when the DIMM is fully seated in the socket.

公开(公告)号：US20210021089A1

公开(公告)日：2021-01-21

申请号：US17031800

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS

IPC: H01R13/66 ,  H01R13/635 ,  H01R12/73

Abstract: An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first electrical circuit component embedded in a latch of the DIMM socket. The first electrical circuit component has a first exposed electrical contact that is to contact or not contact a second exposed electrical contact of a second electrical circuit component that is embedded in a housing of the socket depending on whether a corner of a DIMM is or is not properly inserted into the DIMM socket.

公开(公告)号：US20200226045A1

公开(公告)日：2020-07-16

申请号：US16827974

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Dat T. LE ,  George VERGIS

IPC: G06F11/30 ,  G06F11/32 ,  G06F11/07 ,  G06F1/30

Abstract: A method and apparatus to detect, initialize and isolate a non-operating memory module in a system without physically removing the memory module from the system is provided. The memory module includes a power management integrated circuit to provide power to a memory integrated circuit on the memory module. During initialization of the memory module, if an error log stored in a non-volatile memory in the memory module indicates a fatal error condition from a prior power cycle, the memory module is electrically isolated.

公开(公告)号：US20200027500A1

公开(公告)日：2020-01-23

申请号：US16584724

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  Wei P. CHEN ,  Suresh CHITTOR ,  George VERGIS

IPC: G11C11/406 ,  G06F13/16 ,  G01K13/00

Abstract: Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.

公开(公告)号：US20190354132A1

公开(公告)日：2019-11-21

申请号：US16429872

申请日：2019-06-03

Applicant: Intel Corporation

Inventor： George VERGIS ,  Kuljit S. BAINS ,  Bill NALE

IPC: G06F1/06 ,  G06F13/42

Abstract: Examples include techniques to mirror a command/address or interpret command/address logic at a memory device. A memory device located on a dual in-line memory module (DIMM) may include circuitry having logic capable of receiving a command/address signal and mirror a command/address or interpret command/address logic indicated in the command/address signal based on one or more strap pins for the memory device.

公开(公告)号：US20190042162A1

公开(公告)日：2019-02-07

申请号：US16104040

申请日：2018-08-16

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Suneeta SAH ,  George VERGIS ,  Dimitrios ZIAKAS ,  Bill NALE ,  Chong J. ZHAO ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.