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    SLOW WAVE STRUCTURE FOR MILLIMETER WAVE ANTENNAS
    61.
    发明申请
    SLOW WAVE STRUCTURE FOR MILLIMETER WAVE ANTENNAS 有权

    公开(公告)号：US20220037803A1

    公开(公告)日：2022-02-03

    申请号：US17402916

    申请日：2021-08-16

    Applicant: Intel Corporation

    Inventor： Zhichao Zhang ,  Jiwei Sun ,  Kemal Aygun

    IPC: H01Q21/24 ,  H05K1/02

    Abstract: Length matching and phase matching between circuit paths of differing lengths is disclosed. Two signals are specified to arrive at respective path destinations at a predetermined time and with a predetermined phase. An IC provides a first electronic signal over a first conductive path to a first destination and a second electronic signal over a second conductive path to a second destination. A first slow wave structure comprises the first conductive path and a second slow wave structure comprises the second conductive path. The effective relative permittivity of the first slow wave structure is tuned such that the first electronic signal arrives at its destination at a first time and at a first phase, and the effective relative permittivity of the second slow wave structure is tuned such that the second electronic signal arrives at its destination at a second time and at a second phase.

    Bridge die design for high bandwidth memory interface
    63.
    发明授权
    Bridge die design for high bandwidth memory interface 有权

    公开(公告)号：US11094633B2

    公开(公告)日：2021-08-17

    申请号：US16305758

    申请日：2016-06-30

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim ,  Jackie C. Preciado

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

    Abstract: A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.

    Package substrates with magnetic build-up layers
    64.
    发明授权
    Package substrates with magnetic build-up layers 有权

    公开(公告)号：US11081434B2

    公开(公告)日：2021-08-03

    申请号：US16993112

    申请日：2020-08-13

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

    IPC: H01L23/49 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/68

    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

    Chip-to-chip interconnect with embedded electro-optical bridge structures
    66.
    发明授权
    Chip-to-chip interconnect with embedded electro-optical bridge structures 有权

    公开(公告)号：US10416378B2

    公开(公告)日：2019-09-17

    申请号：US15979382

    申请日：2018-05-14

    Applicant: Intel Corporation

    Inventor： Zhichao Zhang ,  Kemal Aygun ,  Robert L. Sankman

    IPC: G02B6/12 ,  G02B6/42 ,  G02B6/43

    Abstract: Techniques and mechanisms for providing a bridge between integrated circuit (IC) chips. In an embodiment, the bridge device comprises a semiconductor substrate having disposed thereon contacts to couple the bridge device to two IC chips. Circuit structures and photonic structures of a bridge link are integrated with the substrate. The structures include an optical waveguide coupled between an electrical-to-optical signal conversion mechanism and an optical-to-electrical conversion mechanism. The bridge device converts signaling from an electrical domain to an optical domain and back to an electrical domain. In another embodiment, optical signals received via different respective contacts of an IC chip are converted by the bridge device, where the optical signals are multiplexed with each other and variously propagated with the same optical waveguide.

    Ground via clustering for crosstalk mitigation
    67.
    发明授权
    Ground via clustering for crosstalk mitigation 有权

    公开(公告)号：US10396022B2

    公开(公告)日：2019-08-27

    申请号：US16026824

    申请日：2018-07-03

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

    IPC: H01L21/48 ,  H01L23/498

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

    METHODS OF FORMING HYBRID SOCKET STRUCTURES FOR PACKAGE INTERCONNECT APPLICATIONS AND STRUCTURES FORMED THEREBY
    68.
    发明申请
    METHODS OF FORMING HYBRID SOCKET STRUCTURES FOR PACKAGE INTERCONNECT APPLICATIONS AND STRUCTURES FORMED THEREBY 审中-公开

    公开(公告)号：US20190101961A1

    公开(公告)日：2019-04-04

    申请号：US15720484

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Kemal Aygun ,  Zhichao Zhang ,  Cemil Geyik ,  Guneet Kaur

    IPC: G06F1/18 ,  H05K7/14 ,  H01R13/10 ,  H05K3/40

    Abstract: Methods/structures of forming package structures are described. Those methods/structures may include a conductive pin comprising: a cantilever beam portion physically coupled with a first side of a package substrate; a contact pin portion, wherein a terminal end of the contact pin portion is physically and electrically coupled to a board; a housing structure comprising a housing cavity, wherein the contact pin portion is disposed at least partially within the housing cavity; and a conductive material disposed on housing sides and/or adjacent a surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements for either double data rate (DDR) and/or peripheral component interface express (PCIe) interfaces.

    Coupled vias for channel cross-talk reduction
    69.
    发明授权
    Coupled vias for channel cross-talk reduction 有权

    公开(公告)号：US10103054B2

    公开(公告)日：2018-10-16

    申请号：US13802011

    申请日：2013-03-13

    Applicant: INTEL CORPORATION

    Inventor： Zhichao Zhang ,  Zhiguo Qian ,  Tolga Memioglu ,  Kemal Aygun

    IPC: H05K7/10 ,  H05K7/12 ,  H01L21/768 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50

    Abstract: Capacitively coupled vertical transitions are configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.

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