公开(公告)号：US09367114B2

公开(公告)日：2016-06-14

申请号：US13793037

申请日：2013-03-11

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有多个核心的核心域和具有第一逻辑的功率控制器，该第一逻辑接收第一请求以将核心域的第一核心的工作电压增加到第二电压，以指示电压 调节器将工作电压增加到临时电压，然后指示电压调节器将工作电压增加到第二电压。 描述和要求保护其他实施例。

公开(公告)号：US11029744B2

公开(公告)日：2021-06-08

申请号：US15857802

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Esfir Natanzon ,  Doron Rajwan ,  Eliezer Weissmann ,  Dorit Shapira ,  Lily P. Looi ,  Bart Plackle ,  Nadav Shulman

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/20 ,  G06F11/30 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3206

Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

公开(公告)号：US20190354155A1

公开(公告)日：2019-11-21

申请号：US16527150

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC: G06F1/28 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3206

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US10474218B2

公开(公告)日：2019-11-12

申请号：US16223794

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F12/00 ,  G06F1/3234 ,  G06F12/0864 ,  G06F12/084 ,  G06F1/28 ,  G06F12/0802 ,  G06F1/3287 ,  G06F12/0846

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US10228755B2

公开(公告)日：2019-03-12

申请号：US15281806

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Ankush Varma ,  Assaf Ganor ,  Nir Rosenzweig ,  David M. Pawlowski ,  Arik Gihon ,  Nadav Shulman

IPC: G06F1/28 ,  G06F1/32 ,  G06F1/3296

Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.

公开(公告)号：US20190011975A1

公开(公告)日：2019-01-10

申请号：US16044994

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/32 ,  G06F12/0846 ,  G06F1/28 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US09996135B2

公开(公告)日：2018-06-12

申请号：US15157553

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC: G06F1/32 ,  G06F1/28 ,  G06F1/26

CPC classification number: G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US09995791B2

公开(公告)日：2018-06-12

申请号：US15357312

申请日：2016-11-21

Applicant: INTEL CORPORATION

Inventor： Efraim Rotem ,  Nir Rosenzweig ,  Jeffrey A. Carlson ,  Philip R. Lehwalder ,  Nadav Shulman ,  Doron Rajwan

IPC: G01R19/252 ,  G01R31/36 ,  G01R21/133 ,  G01R22/10

CPC classification number: G01R31/3648 ,  G01R21/133 ,  G01R22/10 ,  G01R31/3624

Abstract: Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

公开(公告)号：US20180059763A1

公开(公告)日：2018-03-01

申请号：US15250123

申请日：2016-08-29

Applicant: Intel Corporation

Inventor： Ariel Gur ,  Daniel J Ragland ,  Ofer Nathan ,  Nadav Shulman ,  Esfir Natanzon

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3296

Abstract: A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

公开(公告)号：US09904339B2

公开(公告)日：2018-02-27

申请号：US14482148

申请日：2014-09-10

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Esfir Natanzon ,  Nir Rosenzweig

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.