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公开(公告)号：US11989074B2
公开(公告)日：2024-05-21
申请号：US17354821
申请日：2021-06-22
Applicant: Intel Corporation
Inventor： Dorit Shapira , Anand Enamandram , Daniel Cartagena , Krishnakanth Sistla , Jorge P. Rodriguez , Efraim Rotem , Nir Rosenzweig
IPC: G06F1/32 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F1/3287 , G06F1/3296 , H03M1/12
CPC classification number: G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/3296 , H03M1/12
Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.
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公开(公告)号：US11543878B2
公开(公告)日：2023-01-03
申请号：US17042804
申请日：2018-05-01
Applicant: Intel Corporation
Inventor： Efraim Rotem , Eliezer Weissmann , Eric Dehaemer , Alexander Gendler , Nadav Shulman , Krishnakanth Sistla , Nir Rosenzweig , Ankush Varma , Ariel Szapiro , Arye Albahari , Ido Melamed , Nir Misgav , Vivek Garg , Nimrod Angel , Adwait Purandare , Elkana Korem
IPC: G06F1/32 , G06F9/4401 , G06F1/329 , G06F1/3206 , G06F9/30 , G06F9/48
Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.
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公开(公告)号：US20220283619A1
公开(公告)日：2022-09-08
申请号：US17824984
申请日：2022-05-26
Applicant: Intel Corporation
Inventor： Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nir Rosenzweig , Yoni Aizik
IPC: G06F1/324 , G06F1/3296
Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.
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公开(公告)号：US11435816B2
公开(公告)日：2022-09-06
申请号：US17215104
申请日：2021-03-29
Applicant: Intel Corporation
Inventor： Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Nir Rosenzweig , Eric Distefano , Ishmael F. Santos , James G. Hermerding, II
IPC: G06F1/00 , G06F1/3296 , G06F1/3228 , G06F9/30 , G06F1/324
Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
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公开(公告)号：US20220197361A1
公开(公告)日：2022-06-23
申请号：US17563605
申请日：2021-12-28
Applicant: Intel Corporation
Inventor： Alexander Gendler , Efraim Rotem , Nir Rosenzweig , Krishnakanth V. Sistla , Ashish V. Choubal , Ankush Varma
IPC: G06F1/324 , G06F1/3206 , G06F1/3234 , G06F1/3287 , G06F1/3296 , G06F1/26
Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
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Patent Agency Ranking
公开(公告)号：US10379596B2
公开(公告)日：2019-08-13
申请号：US15227040
申请日：2016-08-03
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Nir Rosenzweig , Efraim Rotem , Yoav Ben-Raphael , Alon Naveh
IPC: G06F1/3206 , G06F1/3287 , G06F1/3296
Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.
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公开(公告)号：US09760160B2
公开(公告)日：2017-09-12
申请号：US14722518
申请日：2015-05-27
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Efraim Rotem , Hisham Abu Salah , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Gal Leibovich , Yevgeni Sabin , Shay Levy
CPC classification number: G06F1/3287 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
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公开(公告)号：US09348401B2
公开(公告)日：2016-05-24
申请号：US13926025
申请日：2013-06-25
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Efraim Rotem , Paul Diefenbaugh , Guy Therien , Nir Rosenzweig
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3243 , G06F1/3293 , Y02D10/122 , Y02D10/126 , Y02D10/152
Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括各自独立地执行指令的多个核心以及耦合到多个核心的功率控制单元（PCU），以控制处理器的功率消耗。 PCU可以包括映射逻辑以从操作系统（OS）接收性能标度值，并且至少部分地基于性能标度值来计算动态性能 - 频率映射。 描述和要求保护其他实施例。
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公开(公告)号：US11815979B2
公开(公告)日：2023-11-14
申请号：US16633120
申请日：2017-08-22
Applicant: Intel Corporation
Inventor： Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Yoni Aizik , Esfir Natanzon , Nir Rosenzweig , Nadav Shulman , Bart Plackle
CPC classification number: G06F1/329 , G06F9/4893
Abstract: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
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公开(公告)号：US20230359263A1
公开(公告)日：2023-11-09
申请号：US18353790
申请日：2023-07-17
Applicant: Intel Corporation
Inventor： Alexander Gendler , Efraim Rotem , Nir Rosenzweig , Krishnakanth V. Sistla , Ashish V. Choubal , Ankush Varma
IPC: G06F1/324 , G06F1/3296 , G06F1/3234 , G06F1/3287 , G06F1/3206 , G06F1/26
CPC classification number: G06F1/324 , G06F1/26 , G06F1/3206 , G06F1/3243 , G06F1/3287 , G06F1/3296 , G06F1/3203
Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.
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