公开(公告)号：US20150286261A1

公开(公告)日：2015-10-08

申请号：US14245301

申请日：2014-04-04

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans M. Jacobson ,  Augusto J. Vega

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24

Abstract: Embodiments relate to storing data in memory. An aspect includes applying a power savings technique to at least a subset of a processor. Pending work items scheduled to be executed by the processor are monitored. The pending work items are grouped based on the power savings technique. The grouping includes delaying a scheduled execution time of at least one of the pending work items to increase an overall number of clock cycles that the power savings technique is applied to the processor. It is determined that an execution criteria has been met. The pending work items are executed based on the execution criteria being met and the grouping.

Abstract translation: 实施例涉及将数据存储在存储器中。 一个方面包括将功率节省技术应用于处理器的至少一个子集。 计划由处理器执行的待处理工作项目被监视。 基于省电技术对待处理的工作项进行分组。 该分组包括延迟至少一个未决工作项目的预定执行时间，以增加将功率节省技术应用于处理器的时钟周期的总数。 确定已经满足执行标准。 待处理的工作项目将根据满足的执行标准和分组执行。

公开(公告)号：US20150082070A1

公开(公告)日：2015-03-19

申请号：US14026472

申请日：2013-09-13

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Hans Jacobson ,  Victor Zyuban

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/26 ,  Y02D10/171 ,  Y02D50/20

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request.

公开(公告)号：US20140229776A1

公开(公告)日：2014-08-14

申请号：US13765320

申请日：2013-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Alan Gara ,  Hans M. Jacobson

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G01R31/30 ,  G01R31/3171 ,  G01R31/318525 ,  G11C29/06 ,  G11C2029/0409

Abstract: An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.

Abstract translation: 用于检测电路中硬错误的装置包括存储装置和处理电路。 存储器中存储有测试数据和正常数据。 处理电路包括与至少一组输入锁存器和至少一组输出锁存器串联的组合逻辑。 该装置包括测试控制模块，该测试控制模块被配置为控制处理电路，以阻止通过处理电路的正常数据流，并且通过处理电路运行测试数据，同时使处理电路处于应力状态。

公开(公告)号：US08796047B2

公开(公告)日：2014-08-05

申请号：US14161896

申请日：2014-01-23

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Eren Kursun ,  Jude A. Rivers ,  Victor Zyuban

IPC: H01L25/00 ,  H01L21/66 ,  H01L21/48 ,  H01L21/768 ,  G01R31/317

CPC classification number: H01L22/20 ,  G01R31/3172 ,  G01R31/31724 ,  G06F11/20 ,  H01L21/485 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/22 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

Abstract translation: 一方面，公开了一种通过应用于电子封装的三维（3D）集成来增强半导体芯片工艺变化性和寿命可靠性的方法。 还提供了用于实施本发明的方法的装置。 在另一方面，公开了一种通过应用于电子封装的三维（3D）集成来增强半导体芯片工艺变化性和寿命可靠性的方法和片上控制器。 还提供了用于实现本发明的方法的片上可靠性/可变性控制器布置。 在另一方面，制造和测试每个包括多个小芯片的基底半导体芯片。 对于具有至少一个非功能小芯片的基底半导体芯片，至少一个修复半导体芯片被垂直堆叠。 形成功能性多芯片组件，其提供与所有小芯片功能性的基础半导体芯片相同的功能。

公开(公告)号：US11966776B2

公开(公告)日：2024-04-23

申请号：US17305784

申请日：2021-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aporva Amarnath ,  Augusto Vega ,  Alper Buyuktosunoglu ,  Hubertus Franke ,  John-David Wellman ,  Pradip Bose

IPC: G06F9/46 ,  G06F9/445 ,  G06F9/48 ,  G06N20/00

CPC classification number: G06F9/4881 ,  G06F9/44505 ,  G06F9/485 ,  G06N20/00

Abstract: Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

公开(公告)号：US11734084B2

公开(公告)日：2023-08-22

申请号：US18150894

申请日：2023-01-06

Applicant: International Business Machines Corporation

Inventor： Augusto Vega ,  Alper Buyuktosunoglu ,  Pradip Bose ,  Vaidyanathan Srinivasan ,  Ranjal Gautham Shenoy

IPC: G06F9/50 ,  G06N20/00 ,  G06N5/043

CPC classification number: G06F9/5083 ,  G06F9/5044 ,  G06F9/5061 ,  G06N20/00 ,  G06N5/043

Abstract: Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.

公开(公告)号：US11630152B2

公开(公告)日：2023-04-18

申请号：US17192164

申请日：2021-03-04

Applicant: International Business Machines Corporation

Inventor： Pradip Bose ,  Alper Buyuktosunoglu ,  Schuyler Eldridge ,  Karthik V. Swaminathan ,  Yazhou Zu

IPC: G01R31/3183 ,  G01R31/317 ,  G06F30/00

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

公开(公告)号：US10831543B2

公开(公告)日：2020-11-10

申请号：US16194252

申请日：2018-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nandhini Chandramoorthy ,  Karthik V. Swaminathan ,  Ramon Bertran Monfort ,  Alper Buyuktosunoglu ,  Pradip Bose

IPC: G06F9/50 ,  G06F9/48

Abstract: Applications on different processing elements have different characteristics such as latency versus bandwidth sensitivity, memory level parallelism, different memory access patterns and the like. Interference between applications due to contention at different sources leads to different effects on performance and is quantified. A method for contention-aware resource provisioning in heterogeneous processors includes receiving stand-alone performance statistics for each processing element for a given application. Multi-core performance slowdown can be computed from the received stand-alone performance statistics. When a request to provision an application on the heterogeneous processors is received, application performance requirements of the application can be determined and a bandwidth for the application can be provisioned based on the application performance requirements and the computed multi-core performance slowdown parameter.

公开(公告)号：US20200168290A1

公开(公告)日：2020-05-28

申请号：US16774505

申请日：2020-01-28

Applicant: International Business Machines Corporation

Inventor： Alper Buyuktosunoglu ,  Swagath Venkataramani ,  Rajiv Joshi ,  Karthik V. Swaminathan ,  Schuyler Eldridge ,  Pradip Bose

IPC: G11C29/50 ,  G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.

公开(公告)号：US20200159586A1

公开(公告)日：2020-05-21

申请号：US16194252

申请日：2018-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nandhini Chandramoorthy ,  Karthik V. Swaminathan ,  Ramon Bertran Monfort ,  Alper Buyuktosunoglu ,  Pradip Bose

IPC: G06F9/50

Abstract: Applications on different processing elements have different characteristics such as latency versus bandwidth sensitivity, memory level parallelism, different memory access patterns and the like. Interference between applications due to contention at different sources leads to different effects on performance and is quantified. A method for contention-aware resource provisioning in heterogeneous processors includes receiving stand-alone performance statistics for each processing element for a given application. Multi-core performance slowdown can be computed from the received stand-alone performance statistics. When a request to provision an application on the heterogeneous processors is received, application performance requirements of the application can be determined and a bandwidth for the application can be provisioned based on the application performance requirements and the computed multi-core performance slowdown parameter.