公开(公告)号：US09501333B2

公开(公告)日：2016-11-22

申请号：US14143783

申请日：2013-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Ahn ,  Luis H. Ceze ,  Dong Chen Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmacht

IPC: G06F9/52 ,  G06F12/08

CPC classification number: G06F9/524 ,  G06F12/08

Abstract: A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

公开(公告)号：US20160011996A1

公开(公告)日：2016-01-14

申请号：US14701371

申请日：2015-04-30

Applicant: International Business Machines Corporation

Inventor： Sameh Asaad ,  Ralph E. Bellofatto ,  Michael A. Blocksome ,  Matthias A. Blumrich ,  Peter Boyle ,  Jose R. Brunheroto ,  Dong Chen ,  Chen-Yong Cher ,  George L. Chiu ,  Norman Christ ,  Paul W. Coteus ,  Kristan D. Davis ,  Gabor J. Dozsa ,  Alexandre E. Eichenberger ,  Noel A. Eisley ,  Matthew R. Ellavsky ,  Kahn C. Evans ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Alan Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Michael K. Gschwind ,  John A. Gunnels ,  Shawn A. Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Todd A. Inglett ,  Brant L. Knudson ,  Gerard V. Kopcsay ,  Sameer Kumar ,  Amith R. Mamidala ,  James A. Marcella ,  Mark G. Megerian ,  Douglas R. Miller ,  Samuel J. Miller ,  Adam J. Muff ,  Michael B. Mundy ,  John K. O'Brien ,  Kathryn M. O'Brien ,  Martin Ohmacht ,  Jeffrey J. Parker ,  Ruth J. Poole ,  Joseph D. Ratterman ,  Valentina Salapura ,  David L. Satterfield ,  Robert M. Senger ,  Burkhard Steinmacher-Burow ,  William M. Stockdell ,  Craig B. Stunkel ,  Krishnan Sugavanam ,  Yutaka Sugawara ,  Todd E. Takken ,  Barry M. Trager ,  James L. Van Oosten ,  Charles D. Wait ,  Robert E. Walkup ,  Alfred T. Watson ,  Robert W. Wisniewski ,  Peng Wu

IPC: G06F13/28 ,  G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06F12/08

CPC classification number: G06F13/287 ,  G06F9/06 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3885 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/1027 ,  G06F15/17381 ,  G06F15/17387 ,  G06F15/76 ,  G06F15/8069 ,  G06F2212/1016 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6032 ,  Y02D10/13 ,  Y02D10/14

Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Abstract translation: 100 petaflop规模的多千兆高效并行超级计算机包括基于片上系统技术的节点架构，其中每个处理节点包括单个专用集成电路（ASIC）。 ASIC节点通过五维环面网络互连，最优化节点之间的分组通信的吞吐量并最小化等待时间。 网络实现集体网络和提供全局障碍和通知功能的全球异步网络。 集成在节点设计中包括一个基于列表的预取器。 存储系统实现事务存储器，线程级别推测和多重切换缓存，同时提高软错误率，并支持DMA功能，允许并行处理消息传递。

公开(公告)号：US20140229776A1

公开(公告)日：2014-08-14

申请号：US13765320

申请日：2013-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pradip Bose ,  Alan Gara ,  Hans M. Jacobson

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G01R31/30 ,  G01R31/3171 ,  G01R31/318525 ,  G11C29/06 ,  G11C2029/0409

Abstract: An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.

Abstract translation: 用于检测电路中硬错误的装置包括存储装置和处理电路。 存储器中存储有测试数据和正常数据。 处理电路包括与至少一组输入锁存器和至少一组输出锁存器串联的组合逻辑。 该装置包括测试控制模块，该测试控制模块被配置为控制处理电路，以阻止通过处理电路的正常数据流，并且通过处理电路运行测试数据，同时使处理电路处于应力状态。

公开(公告)号：US20140207987A1

公开(公告)日：2014-07-24

申请号：US14143783

申请日：2013-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Ahn ,  Luis H. Ceze ,  Dong Chen Chen ,  Alan Gara ,  Philip Heidelberger ,  Martin Ohmacht

IPC: G06F9/52

CPC classification number: G06F9/524 ,  G06F12/08

Abstract: A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

Abstract translation: 多处理器系统支持多种并发模式的推测执行。 投机标识号（ID）从可用数字池中分配给投机线程。 池被分为域，每个域被分配到一种投机模式。 投机模式包括TM，TLS和回滚。 对于中央状态表并使用硬件指针执行ID的分配。 ID用于以高速缓冲存储器中的集合的不同方式写入不同版本的推测结果。

公开(公告)号：US10713043B2

公开(公告)日：2020-07-14

申请号：US15918363

申请日：2018-03-12

Applicant: International Business Machines Corporation

Inventor： Alan Gara ,  David L. Satterfield ,  Robert E. Walkup

IPC: G06F9/30 ,  G06F11/34 ,  G06F11/30 ,  G06F15/173 ,  H04L29/08

Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

公开(公告)号：US10140179B2

公开(公告)日：2018-11-27

申请号：US14973021

申请日：2015-12-17

Applicant: International Business Machines Corporation

Inventor： Alan Gara ,  Dong Chen ,  Philip Heidelberger ,  Martin Ohmacht

IPC: H03M13/00 ,  G06F11/10 ,  H03M1/06 ,  H03M13/13 ,  H03M13/27 ,  H03M13/29

Abstract: A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

公开(公告)号：US20180203693A1

公开(公告)日：2018-07-19

申请号：US15918363

申请日：2018-03-12

Applicant: International Business Machines Corporation

Inventor： Alan Gara ,  David L. Satterfield ,  Robert E. Walkup

IPC: G06F9/30 ,  H04L29/08 ,  G06F11/34 ,  G06F15/173 ,  G06F11/30

CPC classification number: G06F9/30021 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30145 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/348 ,  G06F15/17362 ,  G06F15/17381 ,  G06F15/17393 ,  G06F2201/88 ,  H04L67/10

Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

公开(公告)号：US09921831B2

公开(公告)日：2018-03-20

申请号：US15291351

申请日：2016-10-12

Applicant: International Business Machines Corporation

Inventor： Alan Gara ,  David L. Satterfield ,  Robert E. Walkup

IPC: G06F9/30 ,  G06F11/34 ,  G06F11/30 ,  G06F15/173 ,  H04L29/08

CPC classification number: G06F9/30021 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30145 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/348 ,  G06F15/17362 ,  G06F15/17381 ,  G06F15/17393 ,  G06F2201/88 ,  H04L67/10

Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

公开(公告)号：US09473569B2

公开(公告)日：2016-10-18

申请号：US14800311

申请日：2015-07-15

Applicant: International Business Machines Corporation

Inventor： Alan Gara ,  David L. Satterfield ,  Robert E. Walkup

IPC: G06F15/00 ,  H04L29/08 ,  G06F11/34 ,  G06F11/30 ,  G06F15/173 ,  G06F9/30

CPC classification number: G06F9/30021 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30145 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/348 ,  G06F15/17362 ,  G06F15/17381 ,  G06F15/17393 ,  G06F2201/88 ,  H04L67/10

Abstract: Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

公开(公告)号：US20160110256A1

公开(公告)日：2016-04-21

申请号：US14973021

申请日：2015-12-17

Applicant: International Business Machines Corporation

Inventor： Alan Gara ,  Dong Chen ,  Philip Heidelberger ,  Martin Ohmacht

IPC: G06F11/10 ,  H03M13/00

CPC classification number: G06F11/1076 ,  G06F11/1064 ,  G06F2212/403 ,  H03M1/0687 ,  H03M13/13 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/29 ,  H03M13/616

Abstract: A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.