公开(公告)号：US20150357295A1

公开(公告)日：2015-12-10

申请号：US14830816

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L23/66 ,  H01L29/06 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

公开(公告)号：US09202869B2

公开(公告)日：2015-12-01

申请号：US13890341

申请日：2013-05-09

Applicant: International Business Machines Corporation

Inventor： Natalie B. Feilchenfeld ,  Qizhi Liu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/732

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66287

Abstract: A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures.

Abstract translation: 集电极区域形成在衬底内的绝缘浅沟槽隔离区域之间。 在集电极区域和浅沟槽隔离区域外延生长基材。 基底材料在集电极区域形成基极区域，在浅沟槽隔离区域上形成非本征基极区域。 此外，牺牲发射极结构在基极区域上被图案化，并且在牺牲发射极结构上形成侧壁间隔物。 平面隆起的基底结构在基极区域和外部基极区域外延生长，凸起的基底结构的上层被氧化。 去除牺牲发射极结构以在侧壁间隔物之间​​留出开放空间，并且在侧壁间隔件之间的开放空间内形成发射体。 凸起的基部结构的上层包括将发射器与凸起的基部结构电绝缘的平面绝缘体。

公开(公告)号：US20150303275A1

公开(公告)日：2015-10-22

申请号：US14755862

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Qizhi Liu ,  James S. Nakos

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

CPC classification number: H01L29/66242 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

公开(公告)号：US09159801B2

公开(公告)日：2015-10-13

申请号：US14496242

申请日：2014-09-25

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

IPC: H01L29/66 ,  H01L29/732 ,  H01L29/08 ,  G06F17/50 ,  H01L29/06 ,  H01L29/10 ,  H01L29/735

CPC classification number: H01L29/66303 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/7322 ,  H01L29/735

Abstract: Bipolar junction transistors and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.

Abstract translation: 双极结晶体管和双极结晶体管的设计结构。 双极结晶体管可以包括布置在不同的发射极指中的多个发射极。 形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。 发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。 发射极延伸通过外部基极层和硅化物层与本征基极层接触。 发射器可以在替代型工艺中使用牺牲发射器基座形成。

公开(公告)号：US20150277064A1

公开(公告)日：2015-10-01

申请号：US14224210

申请日：2014-03-25

Applicant: International Business Machines Corporation

Inventor： Zhong-Xiang He ,  Qizhi Liu ,  Ronald G. Meunier ,  Steven M. Shank

IPC: G02B6/42 ,  G02B6/136 ,  G02B6/132 ,  G02B6/122

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/42 ,  G02B2006/121 ,  G02B2006/12119

Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.

Abstract translation: 公开了具有光波导的结构，该光波导具有第一级的第一段和在第一级和高级第二级之间延伸并且还沿第二级延伸的第二段。 具体地，波导包括在第一和第二介电层之间的第一段。 第二电介质层具有沟槽，该沟槽延伸到第一电介质层，并且其一侧位于与第一段的端部横向相邻的位置。 波导还包括从沟槽的底部在与第一部分相邻的一侧上延伸直到并沿着沟槽相对侧上的第二电介质层的顶表面延伸的第二部分。 第三介电层覆盖沟槽中的第二段和第二介电层的顶表面。 还公开了形成这种光电子结构的方法。

公开(公告)号：US20150206746A1

公开(公告)日：2015-07-23

申请号：US14162403

申请日：2014-01-23

Applicant: International Business Machines Corporation

Inventor： David L. Harame ,  Qizhi Liu ,  Edward J. Nowak

IPC: H01L21/02 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: Disclosed are semiconductor structures with monocrystalline semiconductor fins, which are above a trench isolation region in a semiconductor substrate and which can be incorporated into semiconductor device(s). Also disclosed are methods of forming such structures by forming sidewall spacers on opposing sides of mandrels on a dielectric cap layer. Between adjacent mandrels, an opening is formed that extends vertically through the dielectric cap layer and through multiple monocrystalline semiconductor layers into a semiconductor substrate. A portion of the opening within the substrate is expanded to form a trench. This trench undercuts the semiconductor layers and extends laterally below adjacent sidewall spacers on either side of the opening. The trench is then filled with an isolation layer, thereby forming a trench isolation region, and a sidewall image transfer process is performed using the sidewall spacers to form a pair of monocrystalline semiconductor fins above the trench isolation region.

Abstract translation: 公开了具有单晶半导体鳍片的半导体结构，其在半导体衬底中的沟槽隔离区域上方并且可以并入半导体器件中。 还公开了通过在电介质盖层上的心轴的相对侧上形成侧壁间隔来形成这种结构的方法。 在相邻的心轴之间形成开口，其垂直延伸穿过电介质盖层并通过多个单晶半导体层进入半导体衬底。 衬底内的开口的一部分被扩展以形成沟槽。 该沟槽底切半导体层，并且在开口两侧的相邻侧壁间隔物侧向延伸。 然后用隔离层填充沟槽，从而形成沟槽隔离区域，并且使用侧壁间隔物进行侧壁图像转印处理，以在沟槽隔离区域上方形成一对单晶半导体鳍片。

公开(公告)号：US09059252B1

公开(公告)日：2015-06-16

申请号：US14176552

申请日：2014-02-10

Applicant: International Business Machines Corporation

Inventor： Qizhi Liu ,  Steven M. Shank

IPC: H01L21/8236 ,  H01L21/336 ,  H01L21/768

CPC classification number: H01L21/7682 ,  G02B2006/12061 ,  H01L21/76264 ,  H01L21/764 ,  H01L2223/6627

Abstract: Various methods include: forming a first set of trenches in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of trenches each expose the silicon substrate and internal sidewalls of the first oxide; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a cavity corresponding with each of the first set of trenches; and partially filling each cavity with a dielectric, leaving an air gap within each cavity connected with an air gap in an adjacent cavity.

Abstract translation: 各种方法包括：在前体结构中形成第一组沟槽，其具有：具有晶体方向的硅衬底，所述硅衬底基本上与第一氧化物邻接; 覆盖硅衬底的硅锗（SiGe）层; 覆盖SiGe层的硅层; 覆盖硅层的第二氧化物; 以及覆盖所述第二氧化物的牺牲层，其中所述第一组沟槽均暴露所述硅衬底和所述第一氧化物的内侧壁; 底切在与硅衬底的晶体方向垂直的方向上蚀刻硅衬底以形成与第一组沟槽中的每一个相对应的空腔; 并且用电介质部分地填充每个空腔，在与相邻空腔中的气隙连接的每个空腔内留下空气间隙。

公开(公告)号：US09059234B2

公开(公告)日：2015-06-16

申请号：US14059780

申请日：2013-10-22

Applicant: International Business Machines Corporation

Inventor： John J. Benoit ,  James R. Elliott ,  Qizhi Liu

IPC: H01L21/265 ,  H01L21/306 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06 ,  H01L21/465 ,  H01L21/762

CPC classification number: H01L29/7371 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/465 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.

Abstract translation: 公开了沟槽形成技术，其中第一蚀刻工艺形成通过半导体层进入半导体衬底的开口，然后第二蚀刻工艺扩展衬底内部的开口部分以形成沟槽。 然而，在第二蚀刻之前，在开口的底表面处的衬底中形成掺杂区域。 然后，进行第二蚀刻，使得在开口侧壁处的衬底的未掺杂区域以比掺杂区更快的蚀刻速率被蚀刻，从而确保沟槽具有相对高的纵横比。 还公开了一种双极半导体器件形成方法。 该方法结合沟槽形成技术，使得围绕集电极基座形成的沟槽隔离区域具有高纵横比，从而使集电极到基极电容Ccb和集电极电阻Rc都最小化。

公开(公告)号：US20150115399A1

公开(公告)日：2015-04-30

申请号：US14593282

申请日：2015-01-09

Applicant: International Business Machines Corporation

Inventor： Qizhi Liu

IPC: H01L29/735 ,  H01L29/06 ,  H01L29/10 ,  G06F17/50

CPC classification number: H01L29/735 ,  G06F17/5045 ,  H01L21/76224 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/1008 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/73

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A semiconductor material layer is formed on a substrate and a mask layer is formed on the semiconductor material layer. The mask layer is patterned to form a plurality of openings to the semiconductor material layer. After the mask layer is formed and patterned, the semiconductor material layer is etched at respective locations of the openings to define a first trench, a second trench separated from the first trench by a first section of the semiconductor material layer defining a terminal of the bipolar junction transistor, and a third trench separated from the first trench by a second section of the semiconductor material layer defining an isolation pedestal. A trench isolation region is formed at a location in the substrate that is determined at least in part using the isolation pedestal as a positional reference.

Abstract translation: 双极结型晶体管的器件结构，制造方法和设计结构。 在基板上形成半导体材料层，在半导体材料层上形成掩模层。 图案化掩模层以形成到半导体材料层的多个开口。 在掩模层形成和图案化之后，半导体材料层在开口的相应位置被蚀刻以限定第一沟槽，第二沟槽通过半导体材料层的第一部分与第一沟槽分开，该第一部分限定了双极的端子 以及通过半导体材料层的限定隔离基座的第二部分与第一沟槽分离的第三沟槽。 在衬底中的至少部分地使用隔离基座作为位置参考确定的位置处形成沟槽隔离区域。

公开(公告)号：US09006797B2

公开(公告)日：2015-04-14

申请号：US14041983

申请日：2013-09-30

Applicant: International Business Machines Corporation

Inventor： Hanyi Ding ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L29/84 ,  H01H1/00 ,  B81B7/00 ,  G06F17/50 ,  H01P1/12

CPC classification number: H01H1/0036 ,  B81B7/0006 ,  B81B2201/016 ,  G06F17/5063 ,  G06F17/5068 ,  H01P1/127

Abstract: A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method includes forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method includes forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method includes forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method includes forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.

Abstract translation: 提供了微机电系统（MEMS），形成MEMS和设计结构的方法。 该方法包括在衬底上形成包括信号电极和一对电极的共面波导（CPW）。 该方法包括在CPW上形成第一牺牲材料，以及在第一牺牲材料上方和CPW上方的布线层。 该方法包括在布线层上形成第二牺牲材料层，以及围绕第一牺牲材料和第二牺牲材料形成绝缘体材料。 所述方法包括在所述绝缘体材料中形成至少一个通气孔以暴露所述第二牺牲材料的部分，以及通过所述通气孔去除所述第一和第二牺牲材料以形成围绕所述布线层的空腔结构，并且暴露所述信号线和 一对电极在布线层下方。 通气孔用密封材料密封。