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    Clock verification
    62.
    发明授权
    Clock verification 有权
    时钟验证

    公开(公告)号：US09563727B2

    公开(公告)日：2017-02-07

    申请号：US14674555

    申请日：2015-03-31

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari

    IPC: G06F17/50 ,  G01R31/317

    CPC classification number: G06F17/5031 ,  G01R31/31727 ,  G06F17/504 ,  G06F17/5081

    Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

    Abstract translation: 使用基于断言的验证来验证导出时钟的方法和系统。 该方法包括计数在慢时钟的上升沿和下降沿之间（即，在慢时钟的接通阶段）期间发生的快速时钟的全周期或半周期的数量; 计数在慢时钟的下降沿和上升沿之间（即在慢时钟的OFF阶段期间）发生的快时钟的全周期或半周期的数量; 并使用基于断言的验证来验证计数。

    Livelock detection in a hardware design using formal evaluation logic
    65.
    发明授权
    Livelock detection in a hardware design using formal evaluation logic 有权

    公开(公告)号：US11373025B2

    公开(公告)日：2022-06-28

    申请号：US17133294

    申请日：2020-12-23

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F30/3323 ,  G06F30/33 ,  G06F30/333 ,  G06F11/07 ,  G06F11/30 ,  G06F9/30 ,  G06F9/38

    Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.

    CONTROL PATH VERIFICATION OF HARDWARE DESIGN FOR PIPELINED PROCESS
    66.
    发明申请
    CONTROL PATH VERIFICATION OF HARDWARE DESIGN FOR PIPELINED PROCESS 有权

    公开(公告)号：US20210157964A1

    公开(公告)日：2021-05-27

    申请号：US17167698

    申请日：2021-02-04

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Sam Elliott

    IPC: G06F30/3312

    Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.

    OUT-OF-BOUNDS RECOVERY CIRCUIT
    67.
    发明申请
    OUT-OF-BOUNDS RECOVERY CIRCUIT 有权

    公开(公告)号：US20210004287A1

    公开(公告)日：2021-01-07

    申请号：US17028253

    申请日：2020-09-22

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F11/07 ,  G06F30/30

    Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

    Out-of-bounds recovery circuit
    68.
    发明授权
    Out-of-bounds recovery circuit 有权

    公开(公告)号：US10817367B2

    公开(公告)日：2020-10-27

    申请号：US15784746

    申请日：2017-10-16

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F11/00 ,  G06F11/07 ,  G06F30/30 ,  G06F30/392 ,  G06F115/10 ,  G06F117/06

    Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

    FORMAL VERIFICATION TOOL TO VERIFY HARDWARE DESIGN OF MEMORY UNIT
    69.
    发明申请
    FORMAL VERIFICATION TOOL TO VERIFY HARDWARE DESIGN OF MEMORY UNIT 审中-公开

    公开(公告)号：US20200185051A1

    公开(公告)日：2020-06-11

    申请号：US16792582

    申请日：2020-02-17

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G11C29/38 ,  G11C29/44 ,  G11C29/12 ,  G06F11/34 ,  G06F11/30 ,  G06F11/22

    Abstract: Hardware monitors which can be used by a formal verification tool to exhaustively verify a hardware design for a memory unit. The hardware monitors include detection logic to monitor one or more control signals and/or data signals of an instantiation of the memory unit to detect symbolic writes and symbolic reads. In some examples a symbolic write is a write of symbolic data to a symbolic address; and in other examples a symbolic write is a write of any data to a symbolic address. A symbolic read is a read of the symbolic address. The hardware monitors also include assertion verification logic that verifies an assertion that read data corresponding to a symbolic reads matches write data associated with one or more symbolic writes preceding the read.

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