公开(公告)号：US10910325B2

公开(公告)日：2021-02-02

申请号：US15974393

申请日：2018-05-08

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/528 ,  H01L49/02 ,  H01L23/50 ,  H01L23/13 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.

公开(公告)号：US20200168559A1

公开(公告)日：2020-05-28

申请号：US16663853

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522

Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

公开(公告)号：US20200168538A1

公开(公告)日：2020-05-28

申请号：US16662990

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/498 ,  H01L23/495 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00

Abstract: An embedded interconnect bridge includes a backside trace that can be coupled to a power plane within a semiconductor package substrate. The embedded interconnect bridge-backside trace preserves useful package real estate that is near to where multiple dice are to be mounted on the semiconductor package substrate.

公开(公告)号：US20200006247A1

公开(公告)日：2020-01-02

申请号：US16423561

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/552 ,  H01L23/522

Abstract: To overcome the problem of devices in a multi-chip package (MCP) interfering with one another, such as through electromagnetic interference (EMI) and/or radio-frequency interference (RFI), the chip package can include an electrically conductive stiffener that at least partially electrically shields the devices from one another. At least some of the devices can be positioned in respective recesses in the stiffener. In some examples, when the devices are positioned in the recesses, at least one device does not extend beyond a plane defined by a first side of the stiffener. Such shielding can help reduce interference between the devices. Because device-to-device electrical interference can be reduced, devices on the package can be positioned closer to one another, thereby reducing a size of the package. The devices can electrically connect to a substrate via electrical connections that extend through the stiffener.

公开(公告)号：US20190393141A1

公开(公告)日：2019-12-26

申请号：US16402553

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC: H01L23/498 ,  H01L23/66 ,  H01L25/18 ,  H01L23/552 ,  H01L23/00

Abstract: Disclosed embodiments include a stacked multi-chip package that includes two semiconductor package substrates that are spaced apart by a vertical-device stiffener. The vertical-device stiffener provides both connection space for at least one vertical semiconductive device and at least one vertical radio-frequency device, as well as stiffness and form-factor reduction.

公开(公告)号：US20190109122A1

公开(公告)日：2019-04-11

申请号：US15845492

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Seok Ling Lim ,  Kooi Chi Ooi

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01L21/48 ,  H01L23/492 ,  H01L23/538

Abstract: A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.

公开(公告)号：US09972589B1

公开(公告)日：2018-05-15

申请号：US15474293

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Seok Ling Lim ,  Hoay Tien Teoh

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01P3/08 ,  H01L23/528 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/19032 ,  H01P3/082 ,  H01L2224/81 ,  H01L2224/83

Abstract: Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive layer that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit package substrate may have an internal ground plane, a dielectric layer, a microstrip signal layer as the top transmission line layer, a solder resist layer, and a surface conductive layer that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit package substrate may include altering thicknesses of the dielectric and/or solder resist layers to optimize electrical performance by having the microstrip signal layer closer in proximity to the internal ground layer as compared to the surface conductive layer.