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    Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs
    63.
    发明授权
    Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs 有权

    公开(公告)号：US11522048B2

    公开(公告)日：2022-12-06

    申请号：US16361861

    申请日：2019-03-22

    Applicant: Intel Corporation

    Inventor： Cory Bomberger ,  Anand Murthy ,  Mark T. Bohr ,  Tahir Ghani ,  Biswajeet Guha

    IPC: H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

    Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

    Increased transistor source/drain contact area using sacrificial source/drain layer
    64.
    发明授权
    Increased transistor source/drain contact area using sacrificial source/drain layer 有权

    公开(公告)号：US11495672B2

    公开(公告)日：2022-11-08

    申请号：US16023024

    申请日：2018-06-29

    Applicant: INTEL CORPORATION

    Inventor： Dax M. Crum ,  Biswajeet Guha ,  William Hsu ,  Stephen M. Cea ,  Tahir Ghani

    IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

    Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.

    Isolation schemes for gate-all-around transistor devices
    66.
    发明授权
    Isolation schemes for gate-all-around transistor devices 有权

    公开(公告)号：US11335807B2

    公开(公告)日：2022-05-17

    申请号：US16024046

    申请日：2018-06-29

    Applicant: INTEL CORPORATION

    Inventor： Rishabh Mehandru ,  Stephen M. Cea ,  Biswajeet Guha ,  Tahir Ghani ,  William Hsu

    IPC: H01L29/78 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

    NANOWIRE TRANSISTORS AND METHODS OF FABRICATION
    68.
    发明申请
    NANOWIRE TRANSISTORS AND METHODS OF FABRICATION 有权

    公开(公告)号：US20210408289A1

    公开(公告)日：2021-12-30

    申请号：US16914145

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Biswajeet Guha ,  Brian Greene ,  Robin Chao ,  Adam Faust ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

    Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

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