公开(公告)号：US20240332088A1

公开(公告)日：2024-10-03

申请号：US18129617

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Swapnadip Ghosh ,  Chiao-Ti Huang ,  Matthew Prince ,  Jeffrey Miles Tan ,  Ramy Ghostine ,  Anupama Bowonder

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823456 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: One or more transistors may have gate structures with differing sidewall slopes. The gate structures may be over stacks of channel regions in nanosheets (or nanoribbons or nanowires), and the differing gate profiles may correspond to differing electrical characteristics. Transistors with metal gate structures may be tuned by strategically etching the gate structures, for example, using lower etch powers, higher etch temperatures, and/or longer etch durations, to achieve substantially vertical gate profiles.

公开(公告)号：US11521968B2

公开(公告)日：2022-12-06

申请号：US16024671

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Stephen Cea ,  Biswajeet Guha ,  Anupama Bowonder ,  Tahir Ghani

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US11251302B2

公开(公告)日：2022-02-15

申请号：US16640465

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Karthik Jambunathan ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

公开(公告)号：US11374100B2

公开(公告)日：2022-06-28

申请号：US16022502

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Anand Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/167

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer.

公开(公告)号：US11152461B2

公开(公告)日：2021-10-19

申请号：US15983540

申请日：2018-05-18

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Tahir Ghani ,  Stephen M. Cea ,  William Hsu ,  Szuya S Liao ,  Pratik A. Patel

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.

公开(公告)号：US20190355811A1

公开(公告)日：2019-11-21

申请号：US15983540

申请日：2018-05-18

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Tahir Ghani ,  Stephen M. Cea ,  William Hsu ,  SZUYA S. LIAO ,  PRATIK A. PATEL

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.

公开(公告)号：US12237420B2

公开(公告)日：2025-02-25

申请号：US18643632

申请日：2024-04-23

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand S. Murthy ,  Tahir Ghani ,  Anupama Bowonder

IPC: H01L21/00 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230420574A1

公开(公告)日：2023-12-28

申请号：US17847555

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Agrawal ,  Jack T. Kavalieros ,  Rambert Nahm ,  Natalie Briggs ,  Susmita Ghose ,  Glenn Glass ,  Devin R. Merrill ,  Aaron A. Budrevich ,  Shruti Subramanian ,  Biswajeet Guha ,  William Hsu ,  Adedapo A. Oni ,  Rahul Ramamurthy ,  Anupama Bowonder ,  Hsin-Ying Tseng ,  Rajat K. Paul ,  Marko Radosavljevic

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: Techniques are provided herein to form semiconductor devices on a substrate with an alternative crystallographic surface orientation. The techniques are particularly useful with respect to gate-all-around and forksheet transistor configurations. A substrate having a (110) crystallographic surface orientation forms the basis for the growth of alternating types of semiconductor layers. Both n-channel and p-channel transistors may be fabricated using silicon nanoribbons formed from some of the alternating semiconductor layers. The crystallographic surface orientation of the Si nanoribbons will reflect the same crystallographic surface orientation of the substrate, which leads to a higher hole mobility across the Si nanoribbons of the p-channel devices and an overall improved CMOS device performance.

公开(公告)号：US11757037B2

公开(公告)日：2023-09-12

申请号：US17569643

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Karthik Jambunathan ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/7846 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/42392

Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

公开(公告)号：US20230197716A1

公开(公告)日：2023-06-22

申请号：US17559719

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Cory C. Bomberger ,  Anand Murthy ,  Tahir Ghani ,  Ju Nam ,  Anupama Bowonder

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L21/823412 ,  H01L21/823418

Abstract: An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device comprising: a channel structure including a semiconductor material; a gate stack including a metal, the gate stack on the channel structure; a source structure in a first trench at a first side of the gate stack; a drain structure in a second trench at a second side of the gate stack; individual ones of the source structure and the drain structure including a source or drain (source/drain) liner comprising a doped epitaxial layer conformal with a surface of a corresponding one of the first trench and the second trench; a fill structure filling a portion of a corresponding one the first trench and the second trench, the fill structure adjacent to and compositionally different from the source/drain liner; and metal contact structures coupled to respective ones of the source structure and the drain structure.