公开(公告)号：US08648445B2

公开(公告)日：2014-02-11

申请号：US13428540

申请日：2012-03-23

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/223 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。 第一和第二源极/漏极区域相对于彼此间隔开。 至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。 第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

公开(公告)号：US07579245B2

公开(公告)日：2009-08-25

申请号：US11927950

申请日：2007-10-30

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L29/80 ,  H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/402 ,  H01L29/7831

摘要： An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.

摘要翻译： MOS器件包括在半导体层的上表面附近形成在第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开 。 第一导电类型的非均匀掺杂沟道区形成在靠近半导体层的上表面的半导体层中，并且至少部分地在第一和第二源/漏区之间。 绝缘层形成在半导体层的上表面上。 至少部分地在第一和第二源极/漏极区域之间并且在沟道区域的至少一部分上方形成第一栅极，并且至少在绝缘层上形成的至少一部分第二栅极 并且在第一栅极和第二源极/漏极区域之间。 第二栅极的长度远大于第一栅极的长度，第一栅极和第二栅极彼此电隔离。

公开(公告)号：US07138690B2

公开(公告)日：2006-11-21

申请号：US10623983

申请日：2003-07-21

申请人： Zhijian Xie ,  Shuming Xu

发明人： Zhijian Xie ,  Shuming Xu

IPC分类号： H01L29/78

CPC分类号： H01L29/402 ,  H01L23/5225 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： An MOS device is formed comprising a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. The MOS device further comprises a gate formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, and a shielding structure formed proximate the upper surface of the semiconductor layer and between the gate and the second source/drain region, the shielding structure being electrically connected to the first source/drain region, the shielding structure being spaced laterally from the gate and being non-overlapping relative to the gate. In this manner, the MOS device is substantially compatible with a CMOS process technology.

摘要翻译： 形成MOS器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和形成在半导体层中的第二导电类型的第二源极/漏极区域，以及 与第一源极/漏极区间隔开。 MOS器件还包括形成在半导体层的上表面附近并且至少部分地在第一和第二源极/漏极区之间的栅极，以及靠近半导体层的上表面并且在栅极和第二源极/漏极之间形成的屏蔽结构 源极/漏极区域，屏蔽结构电连接到第一源极/漏极区域，屏蔽结构与栅极横向间隔开并且相对于栅极不重叠。 以这种方式，MOS器件与CMOS工艺技术基本兼容。

公开(公告)号：US20050191815A1

公开(公告)日：2005-09-01

申请号：US11116903

申请日：2005-04-28

申请人： Muhammed Shibib ,  Shuming Xu

发明人： Muhammed Shibib ,  Shuming Xu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L23/58 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/402 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

公开(公告)号：US06927453B2

公开(公告)日：2005-08-09

申请号：US10675633

申请日：2003-09-30

申请人： Muhammed Ayman Shibib ,  Shuming Xu

发明人： Muhammed Ayman Shibib ,  Shuming Xu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L23/58 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/402 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

公开(公告)号：US20050156234A1

公开(公告)日：2005-07-21

申请号：US10977732

申请日：2004-10-29

申请人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

发明人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

IPC分类号： H01L21/336 ,  H01L29/40 ,  H01L29/41 ,  H01L29/76 ,  H01L29/78 ,  H01L31/113

CPC分类号： H01L29/402 ,  H01L29/41 ,  H01L29/7835

摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.

摘要翻译： 形成MOS器件，其包括第一导电类型的半导体层，以及形成在靠近半导体层的上表面的半导体层中的第二导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域 相对于彼此间隔开。 在靠近半导体层的上表面的半导体层中至少部分地在第一和第二源/漏区之间形成漂移区。 绝缘层形成在半导体层的上表面的至少一部分上方和漂移区的至少一部分上方。 栅极形成在绝缘层上并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在漂移区的至少一部分上方的绝缘层上的屏蔽结构。 屏蔽结构被配置为使得MOS器件中的热载流子注入劣化量被控制为在漂移区域的上表面上的屏蔽结构的覆盖量的函数。

公开(公告)号：US06908825B2

公开(公告)日：2005-06-21

申请号：US10298418

申请日：2002-11-14

申请人： Shuming Xu ,  Hanhua Feng ,  Pang Dow Foo ,  Bai Xu ,  Uppili Sridhar

发明人： Shuming Xu ,  Hanhua Feng ,  Pang Dow Foo ,  Bai Xu ,  Uppili Sridhar

IPC分类号： H01F17/00 ,  H01L21/02 ,  H01L27/08 ,  H01L21/764

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L27/08

摘要： The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.

摘要翻译： 本发明涉及一种制造集成电路电感器的方法，该集成电路电感器包括硅衬底和硅衬底上的氧化物层。 在一个方面，该方法包括在氧化物层上沉积感应回路，以及在感应回路下面的氧化物层中形成多个孔。 该方法还包括提供邻近孔的多个桥，并且由感应环内的内部区域和氧化物层的外部区域之间的氧化物层的部分提供，而没有感应环路，感应环路被支撑在桥上。 该方法包括在桥下方的硅衬底中形成沟槽，以在感应环路和硅衬底之间提供气隙。

公开(公告)号：US20050077552A1

公开(公告)日：2005-04-14

申请号：US10673539

申请日：2003-09-29

申请人： Frank Baiocchi ,  Bailey Jones ,  Muhammed Shibib ,  Shuming Xu

发明人： Frank Baiocchi ,  Bailey Jones ,  Muhammed Shibib ,  Shuming Xu

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/456

摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.

摘要翻译： 形成MOS器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和形成在半导体层中的第二导电类型的第二源极/漏极区域，以及 与第一源极/漏极区间隔开。 栅极形成在半导体层的上表面附近并且至少部分地形成在第一和第二源/漏区之间。 所述MOS器件还包括至少一个触点，所述至少一个触点包括在所述第一源极/漏极区域的至少一部分上形成并且与所述第一源极/漏极区域的至少一部分电连接的硅化物层，所述硅化物层从所述栅极横向延伸。 触点还包括直接形成在硅化物层上的至少一个绝缘层。

公开(公告)号：US06710416B1

公开(公告)日：2004-03-23

申请号：US10439863

申请日：2003-05-16

申请人： Shuming Xu

发明人： Shuming Xu

IPC分类号： H01L31119

CPC分类号： H01L29/402 ,  H01L21/28114 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7835

摘要： A metal-oxide-semiconductor (MOS) device is formed comprising a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. The MOS device further comprises a first gate formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, the first gate comprising a plurality of sections spaced apart from one another, and a second gate formed proximate the upper surface of the semiconductor layer, the second gate comprising a first end formed between at least two of the plurality of sections of the first gate and a second end opposite the first end formed above at least a portion of the first gate, the second end being wider than the first end, the first and second gates being electrically isolated from one another.

摘要翻译： 形成金属氧化物半导体（MOS）器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和第二导电性的第二源极/漏极区域 形成在半导体层中并与第一源极/漏极区间隔开。 MOS器件还包括形成在半导体层的上表面附近并且至少部分地在第一和第二源/漏区之间的第一栅极，第一栅极包括彼此间隔开的多个部分，第二栅极形成 靠近半导体层的上表面，第二栅极包括形成在第一栅极的多个部分中的至少两个之间的第一端和形成在第一栅极的至少一部分上方的第一端相对的第二端， 第二端比第一端宽，第一和第二栅极彼此电隔离。

公开(公告)号：US06667516B2

公开(公告)日：2003-12-23

申请号：US10186528

申请日：2002-07-01

申请人： Shuming Xu ,  Hanhua Feng ,  Pang-Dow Foo

发明人： Shuming Xu ,  Hanhua Feng ,  Pang-Dow Foo

IPC分类号： H01L2994

CPC分类号： H01L29/66659 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/7835 ,  Y10S438/923

摘要： In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor power handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.