公开(公告)号：US07135935B2

公开(公告)日：2006-11-14

申请号：US10841866

申请日：2004-05-06

申请人： Kyu-Hyoun Kim

发明人： Kyu-Hyoun Kim

IPC分类号： H03K3/03

CPC分类号： H03K3/012 ,  H03K3/0315 ,  H03K3/0322 ,  Y10S331/03

摘要： A ring oscillator has a first logic circuit forming a first loop. The ring oscillator also has a second logic circuit forming a second loop, such that phase interpolation occurs at a node common to the first and second loops. The phase interpolation results in an output signal with a high frequency.

摘要翻译： 环形振荡器具有形成第一回路的第一逻辑电路。 环形振荡器还具有形成第二回路的第二逻辑电路，使得相位插值发生在第一和第二回路共同的节点处。 相位插值导致具有高频率的输出信号。

公开(公告)号：US20050057316A1

公开(公告)日：2005-03-17

申请号：US10841866

申请日：2004-05-06

申请人： Kyu-Hyoun Kim

发明人： Kyu-Hyoun Kim

IPC分类号： H03K3/0231 ,  H03K3/012 ,  H03K3/03 ,  H03B1/00

CPC分类号： H03K3/012 ,  H03K3/0315 ,  H03K3/0322 ,  Y10S331/03

摘要： A ring oscillator has a first logic circuit forming a first loop. The ring oscillator also has a second logic circuit forming a second loop, such that phase interpolation occurs at a node common to the first and second loops. The phase interpolation results in an output signal with a high frequency.

摘要翻译： 环形振荡器具有形成第一回路的第一逻辑电路。 环形振荡器还具有形成第二回路的第二逻辑电路，使得相位插值发生在第一和第二回路共同的节点处。 相位插值导致具有高频率的输出信号。

公开(公告)号：US06847559B2

公开(公告)日：2005-01-25

申请号：US10611255

申请日：2003-07-01

申请人： Reum Oh ,  Woo-Seop Jeong ,  Kyu-Hyoun Kim

发明人： Reum Oh ,  Woo-Seop Jeong ,  Kyu-Hyoun Kim

IPC分类号： H03K19/0175 ,  G11C7/10 ,  G11C11/406 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C7/1084 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4093

摘要： The present invention discloses an input buffer circuit of a synchronous semiconductor memory device comprising a differential amplifier type input buffer and a low current type input buffer, wherein the differential amplifier type input buffer is operated in a normal mode, and the low current type input buffer is operated in a self-refresh mode, thereby decreasing the current flowing through the input buffer in the self-refresh mode. According to the input buffer of the synchronous semiconductor memory device, the current flowing through the input buffer in the self-refresh mode is very small, therefore the power consumption of the synchronous semiconductor memory device can be reduced.

摘要翻译： 本发明公开了一种包括差分放大器型输入缓冲器和低电流型输入缓冲器的同步半导体存储器件的输入缓冲电路，其中差分放大器型输入缓冲器以正常模式工作，低电流型输入缓冲器 在自刷新模式下操作，从而在自刷新模式下减少流过输入缓冲器的电流。 根据同步半导体存储器件的输入缓冲器，在自刷新模式中流过输入缓冲器的电流非常小，因此可以降低同步半导体存储器件的功耗。

公开(公告)号：US08516409B2

公开(公告)日：2013-08-20

申请号：US12944020

申请日：2010-11-11

申请人： Paul W. Coteus ,  Kyu-Hyoun Kim ,  Robert B. Tremaine

发明人： Paul W. Coteus ,  Kyu-Hyoun Kim ,  Robert B. Tremaine

IPC分类号： G06F17/50

CPC分类号： H01L25/0657 ,  G11C5/04 ,  G11C17/143 ,  G11C17/16 ,  G11C29/12 ,  G11C29/785 ,  G11C29/802 ,  G11C2229/763 ,  G11C2229/766 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

摘要： A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.

摘要翻译： 一种用于实现芯片堆叠以在多个裸片上分布逻辑功能的方法和电路，以及提供了通过硅片通过堆叠的半导体器件的裸片识别和备用，以及设置有被摄体电路的设计结构。 管芯堆叠中的每个管芯包括用于实现相应的预定义功能的预定义功能逻辑。 在每个相应的管芯中执行相应的预定义功能，并且将相应的功能结果提供给管芯堆叠中的相邻管芯。 管芯堆叠中的每个管芯包括用于提供管芯识别的逻辑。 通过组合每个管芯上的多个选择的信号来形成操作管芯签名。 使用TSV互连将芯片签名耦合到下一级相邻裸片，其中它与该芯片签名组合。

公开(公告)号：US20120020171A1

公开(公告)日：2012-01-26

申请号：US12840879

申请日：2010-07-21

申请人： Kevin C. Gower ,  Lisa C. Gower ,  Kyu-Hyoun Kim ,  Warren E. Maule

发明人： Kevin C. Gower ,  Lisa C. Gower ,  Kyu-Hyoun Kim ,  Warren E. Maule

IPC分类号： G11C8/18 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2227

摘要： A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

摘要翻译： 具有延迟锁定环（DLL）旁路控制的存储器系统，包括用于访问存储器的方法，包括在存储器件处接收存储器读命令。 存储器件被配置为以DLL关闭模式操作以绕过DLL时钟作为生成读取时钟的输入。 在存储器装置处接收到DLL加电命令，并且响应于接收到DLL加电命令，在存储器件执行DLL初始化处理。 存储器读取命令在以DLL关闭模式操作的存储器件处被服务，在执行DLL初始化过程时，服务与时间重叠。 存储器装置被配置为以模拟DLL操作以利用DLL时钟作为输入，以响应于经过指定的时间段来生成读取时钟。 指定的时间段相对于接收DLL上电命令。

公开(公告)号：US07778042B2

公开(公告)日：2010-08-17

申请号：US12143126

申请日：2008-06-20

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： H05K1/11

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US20090085650A1

公开(公告)日：2009-04-02

申请号：US12325846

申请日：2008-12-01

申请人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

发明人： Jin-Kyoung Jung ,  Jung-Bae Lee ,  Kyu-Hyoun Kim

IPC分类号： G05F3/02

CPC分类号： G05F1/465

摘要： An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

摘要翻译： 提供内部电压产生电路。 半导体器件的内部电压产生电路包括：控制信号发生电路，用于根据多个数据位产生控制信号;比较器，用于将参考电压与内部电压进行比较，以在控制信号失效时产生驱动信号 ，用于当所述控制信号被激活时使所述驱动信号失活的驱动信号控制电路和用于接收外部电源电压并且响应于所述驱动信号产生所述内部电压的内部电压驱动电路。 因此，可以根据半导体器件的数据输入和/或输出位的数量将内部电压转换为参考电压电平或外部电源电压，并且即使当数据输入和/或输出位数 增加，可以提高数据访问速度。

公开(公告)号：US20080247212A1

公开(公告)日：2008-10-09

申请号：US12143126

申请日：2008-06-20

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： G11C5/06

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US07405949B2

公开(公告)日：2008-07-29

申请号：US11603648

申请日：2006-11-22

申请人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

发明人： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

IPC分类号： H05K7/14

CPC分类号： G11C5/063

摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

摘要翻译： 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

公开(公告)号：US07375564B2

公开(公告)日：2008-05-20

申请号：US10716146

申请日：2003-11-18

申请人： Geun-Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

发明人： Geun-Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/135 ,  H03K2005/00208 ,  H03L7/0818

摘要： A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes delay cells having various unit time delays. The number of delay cells is adjusted in response to a shift signal. The delay line receives the external clock signal and outputs an output clock signal. The filter unit generates the shift signal in response to the error control signal. In the delay-locked loop, the front delay cells, which compensate for a delay of an external clock signal having a high frequency, have short unit time delays. The rear delay cells, which compensate for a delay of the external clock signal having a low frequency, have long unit time delays.

摘要翻译： 延迟锁定环包括相位检测器，延迟线和滤波器单元。 相位检测器将外部时钟信号的相位与反馈时钟信号的相位进行比较，并输出相位差作为误差控制信号。 延迟线包括具有各种单位时间延迟的延迟单元。 响应于移位信号调整延迟单元的数量。 延迟线接收外部时钟信号并输出​​输出时钟信号。 滤波器单元响应于误差控制信号产生移位信号。 在延迟锁定环路中，补偿具有高频率的外部时钟信号的延迟的前延迟单元具有较短的单位时间延迟。 补偿具有低频率的外部时钟信号的延迟的后延迟单元具有长的单位时间延迟。