公开(公告)号：US20090313423A1

公开(公告)日：2009-12-17

申请号：US12467529

申请日：2009-05-18

申请人： Dae-Seok Byeon

发明人： Dae-Seok Byeon

IPC分类号： G06F12/02 ,  G11C16/02 ,  G11C16/06 ,  G06F12/00

CPC分类号： G11C11/5621 ,  G11C2211/5646

摘要： Disclosed is a multi-bit flash memory device which includes a memory cell array and a control circuit. The memory cell array has multiple memory cells and multiple flag cells. The control circuit determines whether the flag cells are programmed, based on a reference corresponding to a read margin of the flag cells, and controls a program operation of the memory cells in response to the determination.

摘要翻译： 公开了一种包括存储单元阵列和控制电路的多位闪存装置。 存储单元阵列具有多个存储单元和多个标志单元。 控制电路基于与标志单元的读取余量相对应的基准来确定标志单元是否被编程，并且响应于该确定来控制存储器单元的编程操作。

公开(公告)号：US07508705B2

公开(公告)日：2009-03-24

申请号：US11847980

申请日：2007-08-30

申请人： Dong-Hyuk Chae ,  Dae-Seok Byeon

发明人： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC分类号： G11C16/04

CPC分类号： G11C16/3404

摘要： A method for programming multi-level non-volatile memory including at least one flag cell and a plurality of multi-bit storage cells. Each storage cell stores data of a least significant bit (LSB) and a most significant bit (MSB). The cells are programmed with LSB data such that programmed storage cells have a threshold voltage greater than VR1. The threshold voltage is modified to have a threshold voltage greater than VR2 for a third or fourth value. The cells are programmed with MSB data for a threshold voltage lower than a VR1 for a first value greater than VR1 and lower than VR2 for a second value, greater than VR2 and lower than VR3 for a third value, and greater than VR3 for a fourth value. VR1 is less than VR2 which is less than VR3. The flag cell is programmed to signal whether MSB data has been programmed.

摘要翻译： 一种用于编程包括至少一个标志单元和多个多位存储单元的多级非易失性存储器的方法。 每个存储单元存储最低有效位（LSB）和最高有效位（MSB）的数据。 单元被编程为LSB数据，使得编程的存储单元具有大于VR1的阈值电压。 对于第三或第四值，阈值电压被修改为具有大于VR2的阈值电压。 对于小于VR1的阈值电压，对于小于VR1的第一值并且对于第二值低于VR2的单元，对于第三值，单元格被编程为高于VR2且低于VR3，而对于第四值大于VR3 值。 VR1小于小于VR3的VR2。 标志单元被编程为通知MSB数据是否被编程。

公开(公告)号：US07499327B2

公开(公告)日：2009-03-03

申请号：US11443205

申请日：2006-05-31

申请人： Pan-Suk Kwak ,  Dae-Seok Byeon

发明人： Pan-Suk Kwak ,  Dae-Seok Byeon

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/24 ,  G11C16/0483 ,  G11C16/16

摘要： A NAND flash memory device includes a memory cell array including a plurality of memory cells, a plurality of page buffers, and an isolation circuit connected between the memory cell array and the plurality of page buffers. The isolation circuit comprises a high voltage transistor adapted to disconnect a first bit line connected to the memory cell array from a second bit line connected to the one of the page buffers during an erase operation of the NAND flash memory device. During the read operation, a third bit line arranged in parallel with the second bit line and connected to one of the page buffers is discharged to prevent the page buffer from being damaged due to coupling capacitance between the second and third bit lines.

摘要翻译： NAND闪存器件包括存储单元阵列，该存储单元阵列包括多个存储单元，多个页缓冲器以及连接在存储单元阵列与多个页缓冲器之间的隔离电路。 隔离电路包括高电压晶体管，其适于在NAND闪速存储器件的擦除操作期间将连接到存储单元阵列的第一位线与连接到该页缓冲器之一的第二位线断开。 在读取操作期间，放电与第二位线并联并连接到页面缓冲器之一的第三位线，以防止页缓冲器由于第二位线和第三位线之间的耦合电容而损坏。

公开(公告)号：US07439797B2

公开(公告)日：2008-10-21

申请号：US11605223

申请日：2006-11-29

申请人： Dae-Seok Byeon ,  Dong-Hyuk Chae

发明人： Dae-Seok Byeon ,  Dong-Hyuk Chae

IPC分类号： G05F1/46

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A semiconductor memory device includes a first pump clock generator configured to generate a first pump clock signal based on a power supply voltage. The device also includes a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also includes a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also includes a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also includes a switching unit configured to selectively connect the first charge pump to the second charge pump.

摘要翻译： 半导体存储器件包括被配置为基于电源电压产生第一泵时钟信号的第一泵时钟发生器。 该装置还包括配置成响应于第一泵时钟信号产生第一泵输出电压的第一电荷泵。 该装置还包括配置成基于第一泵输出电压产生第二泵时钟信号的第二泵时钟发生器。 该装置还包括配置成响应于第二泵时钟信号产生第二泵输出电压的第二电荷泵。 该装置还包括配置成选择性地将第一电荷泵连接到第二电荷泵的开关单元。

公开(公告)号：US07439792B2

公开(公告)日：2008-10-21

申请号：US11549411

申请日：2006-10-13

申请人： Pan-Suk Kwak ,  Dae-Seok Byeon

发明人： Pan-Suk Kwak ,  Dae-Seok Byeon

IPC分类号： H03K3/10

CPC分类号： H02M3/07

摘要： A high voltage generation circuit includes a pump clock generation unit configured to generate a pump clock signal in response to a pumping enable signal, a charge pump configured to generate a high voltage on an output in response to the pump clock signal, and a switching unit to selectively couple the output of the charge pump to an output node in response to the pumping enable signal.

摘要翻译： 高压发生电路包括：泵时钟生成单元，被配置为响应于泵浦使能信号而产生泵浦时钟信号;电荷泵，被配置为响应于所述泵浦时钟信号而在输出端产生高电压;以及开关单元 以响应于泵送使能信号选择性地将电荷泵的输出耦合到输出节点。

公开(公告)号：US07414890B2

公开(公告)日：2008-08-19

申请号：US11605227

申请日：2006-11-29

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/04 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  H02M3/07

摘要： A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also comprises a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also comprises a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also comprises a third pump clock generator configured to generate a third pump clock signal based on the first power supply voltage. The device also comprises a third charge pump configured to generate a third pump output voltage in response to the third pump clock signal.

摘要翻译： 半导体存储器件包括被配置为基于第一电源电压产生第一泵时钟信号的第一泵时钟发生器。 该装置还包括配置成响应于第一泵时钟信号产生第一泵输出电压的第一电荷泵。 该装置还包括被配置为基于第一泵输出电压产生第二泵时钟信号的第二泵时钟发生器。 该装置还包括配置成响应于第二泵时钟信号产生第二泵输出电压的第二电荷泵。 该装置还包括配置成基于第一电源电压产生第三泵时钟信号的第三泵时钟发生器。 该装置还包括配置成响应于第三泵时钟信号产生第三泵输出电压的第三电荷泵。

公开(公告)号：US07397706B2

公开(公告)日：2008-07-08

申请号：US11381556

申请日：2006-05-04

申请人： Dae-Seok Byeon ,  Young-Ho Lim

发明人： Dae-Seok Byeon ,  Young-Ho Lim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16

摘要： Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while applying an erasing voltage to a bulk region of memory cells, and verifying the erased states of the memory cells. Pursuant to these methods, the spread of the threshold-voltage distribution profile that may result from deviations of erasure-coupling ratios between memory cells may be reduced.

摘要翻译： 提供擦除闪速存储器件中的数据的方法，其中产生多个字线偏置电压，其包括具有至少两个不同电平的字线偏置电压，通过将不同的字线偏置电压施加到多个字线中的相应字线来擦除数据 同时将擦除电压施加到存储器单元的主体区域，以及验证存储器单元的擦除状态。 根据这些方法，可能会降低可能由存储器单元之间的擦除耦合比的偏差导致的阈值 - 电压分布曲线的扩展。

公开(公告)号：US07392408B2

公开(公告)日：2008-06-24

申请号：US11218420

申请日：2005-09-06

申请人： Seung-Hyun Moon ,  Dae-Seok Byeon

发明人： Seung-Hyun Moon ,  Dae-Seok Byeon

IPC分类号： G06F1/00 ,  G06F1/26

CPC分类号： G11C16/225 ,  H03K19/00369

摘要： A lock-out circuit is adapted to selectively perform a lock-out function in an integrated circuit device. The lock-out function cuts off the supply of an operating voltage to the integrated circuit device whenever a power supply voltage for the device falls below a predetermined detection voltage. However, the lock-out function is disabled whenever the integrated circuit device performs an operation requiring a power supply voltage lower than the predetermined detection voltage.

摘要翻译： 锁定电路适于选择性地执行集成电路装置中的锁定功能。 每当设备的电源电压下降到预定检测电压以下时，锁定功能将切断对集成电路器件的工作电压的供应。 然而，只要集成电路器件执行需要低于预定检测电压的电源电压的操作，禁止锁定功能。

公开(公告)号：US20080123436A1

公开(公告)日：2008-05-29

申请号：US11944834

申请日：2007-11-26

申请人： Dae-Seok Byeon

发明人： Dae-Seok Byeon

IPC分类号： G11C16/06

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3477 ,  G11C16/3486

摘要： In one aspect, a non-volatile NAND-flash semiconductor memory device is provided which is configured to execute at least one of a pre-program operation and a post-program operation before and after an erase operation, respectively. Each of the pre-program and post-program operations includes applying a program voltage to a subset of a plurality of word lines defining a word line block of the memory device.

摘要翻译： 一方面，提供一种非易失性NAND闪存半导体存储器件，其被配置为分别在擦除操作之前和之后执行预编程操作和后编程操作中的至少一个。 预编程和后程序操作中的每一个包括将编程电压应用于限定存储器件的字线块的多个字线的子集。

公开(公告)号：US20080079503A1

公开(公告)日：2008-04-03

申请号：US11605223

申请日：2006-11-29

申请人： Dae-Seok Byeon ,  Dong-Hyuk Chae

发明人： Dae-Seok Byeon ,  Dong-Hyuk Chae

IPC分类号： H03L7/00

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A semiconductor memory device includes a first pump clock generator configured to generate a first pump clock signal based on a power supply voltage. The device also includes a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also includes a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also includes a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also includes a switching unit configured to selectively connect the first charge pump to the second charge pump.