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105 条记录 (耗时 0.029 秒)

    Method and apparatus for selectively performing lock-out function in integrated circuit device
    1.
    发明授权
    Method and apparatus for selectively performing lock-out function in integrated circuit device 有权
    用于在集成电路装置中选择性地执行锁定功能的方法和装置

    公开(公告)号：US07392408B2

    公开(公告)日：2008-06-24

    申请号：US11218420

    申请日：2005-09-06

    申请人： Seung-Hyun Moon ,  Dae-Seok Byeon

    发明人： Seung-Hyun Moon ,  Dae-Seok Byeon

    IPC分类号： G06F1/00 ,  G06F1/26

    CPC分类号： G11C16/225 ,  H03K19/00369

    摘要： A lock-out circuit is adapted to selectively perform a lock-out function in an integrated circuit device. The lock-out function cuts off the supply of an operating voltage to the integrated circuit device whenever a power supply voltage for the device falls below a predetermined detection voltage. However, the lock-out function is disabled whenever the integrated circuit device performs an operation requiring a power supply voltage lower than the predetermined detection voltage.

    摘要翻译： 锁定电路适于选择性地执行集成电路装置中的锁定功能。 每当设备的电源电压下降到预定检测电压以下时，锁定功能将切断对集成电路器件的工作电压的供应。 然而，只要集成电路器件执行需要低于预定检测电压的电源电压的操作，禁止锁定功能。

    Method and apparatus for selectively performing lock-out function in integrated circuit device
    2.
    发明申请
    Method and apparatus for selectively performing lock-out function in integrated circuit device 有权
    用于在集成电路装置中选择性地执行锁定功能的方法和装置

    公开(公告)号：US20060103480A1

    公开(公告)日：2006-05-18

    申请号：US11218420

    申请日：2005-09-06

    申请人： Seung-Hyun Moon ,  Dae-Seok Byeon

    发明人： Seung-Hyun Moon ,  Dae-Seok Byeon

    IPC分类号： H03B1/00

    CPC分类号： G11C16/225 ,  H03K19/00369

    摘要： A lock-out circuit is adapted to selectively perform a lock-out function in an integrated circuit device. The lock-out function cuts off the supply of an operating voltage to the integrated circuit device whenever a power supply voltage for the device falls below a predetermined detection voltage. However, the lock-out function is disabled whenever the integrated circuit device performs an operation requiring a power supply voltage lower than the predetermined detection voltage.

    摘要翻译： 锁定电路适于选择性地执行集成电路装置中的锁定功能。 每当设备的电源电压下降到预定检测电压以下时，锁定功能将切断对集成电路器件的工作电压的供应。 然而，只要集成电路器件执行需要低于预定检测电压的电源电压的操作，禁止锁定功能。

    Resistive memory device and operating method
    4.
    发明授权
    Resistive memory device and operating method 有权
    电阻式存储器件及操作方法

    公开(公告)号：US09355721B2

    公开(公告)日：2016-05-31

    申请号：US14800727

    申请日：2015-07-16

    申请人： Chi-Weon Yoon ,  Hyun-Kook Park ,  Dae-Seok Byeon

    发明人： Chi-Weon Yoon ,  Hyun-Kook Park ,  Dae-Seok Byeon

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C13/00

    CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2013/0092

    摘要： A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.

    摘要翻译： 操作存储器件的方法包括： 通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中 所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压 在第二设定写入间隔期间到第一信号线的第二电压。

    Flash memory device operating at multiple speeds
    5.
    发明授权
    Flash memory device operating at multiple speeds 有权
    闪存设备以多种速度运行

    公开(公告)号：US07957201B2

    公开(公告)日：2011-06-07

    申请号：US12854987

    申请日：2010-08-12

    申请人： Dae-Seok Byeon

    发明人： Dae-Seok Byeon

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C16/30 ,  G11C16/24

    摘要： A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.

    摘要翻译： 操作闪速存储器件的方法包括具有不同操作速度的第一操作模式和第二操作模式。 第一和第二操作模式中的每一个包括位线建立间隔和至少一个附加间隔。 闪存被分成连接到相应的第一和第二R / W电路的第一和第二垫。 在第二操作模式的位线设置间隔期间，闪速存储器以时分方式控制第一和第二R / W电路的操作，以交错第一和第二垫的相应的峰值电流间隔。

    Flash memory device and program method of flash memory device using different voltages
    6.
    发明授权
    Flash memory device and program method of flash memory device using different voltages 有权
    闪存器件和使用不同电压的闪存器件的程序方法

    公开(公告)号：US07852682B2

    公开(公告)日：2010-12-14

    申请号：US11830260

    申请日：2007-07-30

    申请人： Dae-Seok Byeon ,  Young-Ho Lim

    发明人： Dae-Seok Byeon ,  Young-Ho Lim

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.

    摘要翻译： 闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。 一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。 局部电压低于通过电压，等于或高于接地电压。 在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

    INTERNAL VOLTAGE GENERATOR AND CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME
    8.
    发明申请
    INTERNAL VOLTAGE GENERATOR AND CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME 有权
    内部电压发生器及其控制方法及其半导体存储器件及其系统

    公开(公告)号：US20090021985A1

    公开(公告)日：2009-01-22

    申请号：US12175494

    申请日：2008-07-18

    申请人： Dae-Seok Byeon

    发明人： Dae-Seok Byeon

    IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C5/14

    CPC分类号： G11C29/02 ,  G11C5/147 ,  G11C16/30 ,  G11C29/021 ,  G11C29/028

    摘要： An internal voltage of a semiconductor memory device is controlled, where the internal voltage is set according to a reference voltage. The reference voltage is controlled according to first control data to increase the internal voltage to be higher than a target voltage in a power-up operation, and second control data is read. The reference voltage is then controlled according to the second control data to decrease the internal voltage to the target voltage.

    摘要翻译： 控制半导体存储器件的内部电压，其中根据参考电压设置内部电压。 根据第一控制数据控制参考电压，以在上电操作中将内部电压增加到高于目标电压，并且读取第二控制数据。 然后根据第二控制数据控制参考电压，以将内部电压降低到目标电压。

    Semiconductor device including a high voltage generation circuit and method of a generating high voltage
    9.
    发明申请
    Semiconductor device including a high voltage generation circuit and method of a generating high voltage 有权

    公开(公告)号：US20080123417A1

    公开(公告)日：2008-05-29

    申请号：US11605227

    申请日：2006-11-29

    申请人： Dae-Seok Byeon ,  Young-Ho Lim

    发明人： Dae-Seok Byeon ,  Young-Ho Lim

    IPC分类号： G11C16/04 ,  G05F1/10 ,  G11C8/10

    CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  H02M3/07

    摘要： A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also comprises a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also comprises a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also comprises a third pump clock generator configured to generate a third pump clock signal based on the first power supply voltage. The device also comprises a third charge pump configured to generate a third pump output voltage in response to the third pump clock signal.