公开(公告)号：US20090294892A1

公开(公告)日：2009-12-03

申请号：US12418808

申请日：2009-04-06

申请人： Amit Paul ,  Mohamed N. Darwish ,  Jun Zeng

发明人： Amit Paul ,  Mohamed N. Darwish ,  Jun Zeng

IPC分类号： H01L29/06 ,  H01L29/861

CPC分类号： H01L29/0649 ,  H01L29/0692 ,  H01L29/408 ,  H01L29/7811 ,  H01L29/8611

摘要： A high-voltage termination structure includes a peripheral voltage-spreading network. One or more trench structures are connected at least partly in series between first and second power supply voltages. The trench structures include first and second current-limiting structures connected in series with a semiconductor material, and also includes permanent charge in a trench-wall dielectric. The current-limiting structures in the trench structures are jointly connected in a series-parallel ladder configuration. The current-limiting structures, in combination with the semiconductor material, provide a voltage distribution between the core portion and the edge portion.

摘要翻译： 高压端接结构包括外围电压分布网络。 一个或多个沟槽结构至少部分地串联连接在第一和第二电源电压之间。 沟槽结构包括与半导体材料串联连接的第一和第二限流结构，并且还包括在沟槽壁电介质中的永久电荷。 沟槽结构中的电流限制结构以串联 - 并联梯形结构共同连接。 与半导体材料组合的限流结构在芯部分和边缘部分之间提供电压分布。

公开(公告)号：US20090085099A1

公开(公告)日：2009-04-02

申请号：US11866353

申请日：2007-10-02

申请人： Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

发明人： Shih Tzung Su ,  Jun Zeng ,  Poi Sun ,  Kao Way Tu ,  Tai Chiang Chen ,  Long Lv ,  Xin Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： In accordance with the invention a vertical power trench MOSFET semiconductor device comprises P+ body and N+ source diffusions shorted together to prevent second breakdown caused by a parasitic bipolar transistor. The device is manufactured in accordance with a process comprising the steps of: providing a heavily doped N+ silicon substrate; utilizing a first, trench, mask to define a plurality of openings comprising a trench gate and a termination; creating P+ body and N+ source area formations by ion implantation without any masks; utilizing a second, contact, mask to define a gate bus area; and utilizing a third metal mask to separate source metal and gate bus metal and remove metal from a portion of the termination, whereby only three masks are utilized to form the semiconductor device.

摘要翻译： 根据本发明，垂直功率沟槽MOSFET半导体器件包括P +体和N +源极扩散在一起短路以防止由寄生双极晶体管引起的第二次击穿。 该装置根据包括以下步骤的方法制造：提供重掺杂的N +硅衬底; 利用第一沟槽掩模来限定包括沟槽栅极和终端的多个开口; 通过没有任何掩模的离子注入产生P +体和N +源区形成; 利用第二接触掩模来定义一个门总线区域; 并且利用第三金属掩模来分离源极金属和栅极总线金属并从终端的一部分去除金属，由此仅使用三个掩模来形成半导体器件。

公开(公告)号：US07501323B2

公开(公告)日：2009-03-10

申请号：US11104164

申请日：2005-04-12

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L21/336

CPC分类号： H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.

摘要翻译： 制造功率MOSFET的方法包括在半导体层中形成沟槽，形成衬底沟槽的栅极电介质层，在沟槽的下部形成栅极导电层，形成电介质层以填充该沟槽的上部 沟。 去除与电介质层横向相邻的半导体层的部分，使得其上部从半导体层向外延伸。 间隔件横向邻近介质层的向外延伸的上部形成，间隔件用作用于限定源/体接触区域的自对准掩模。

公开(公告)号：US20080207613A1

公开(公告)日：2008-08-28

申请号：US10585916

申请日：2005-01-12

申请人： Michelle Leanne Styles ,  Jun Zeng ,  Herbert Rudolf Treutlein ,  Andrew Frederick Wilks ,  Marcel Robert Kling ,  Christopher John Burns ,  Xianyong Bu

发明人： Michelle Leanne Styles ,  Jun Zeng ,  Herbert Rudolf Treutlein ,  Andrew Frederick Wilks ,  Marcel Robert Kling ,  Christopher John Burns ,  Xianyong Bu

IPC分类号： A61K31/5377 ,  C07D403/04 ,  C07D403/14 ,  C07D401/04 ,  C07D407/14 ,  C07D409/14 ,  C07D413/14 ,  A61P37/06 ,  C07D401/14 ,  C07D235/04 ,  A61K31/497 ,  A61K31/4439 ,  A61K31/506 ,  A61K31/4184

CPC分类号： C07D403/04 ,  C07D235/30 ,  C07D241/20 ,  C07D401/12 ,  C07D401/14 ,  C07D405/12

摘要： A compound of the general formula (I) or pharmaceutically acceptable prodrugs, salts, hydrates, solvates, crystal forms or diastereomers thereof, wherein A represents a variety of six membered nitrogen containing heterocyclic rings, Q is a bond, halogen, C1-4 alkyl, O, S, SO2, CO or CS and X1, X2, X3 and X4 are optionally substituted by 9 specific substituents or one can be nitrogen. Compositions comprising a carrier and at least one compound of formula (I) are also provided. Further provided are methods of treating tyrosine kinase-associated disease states by administering a compound of formula (I) and methods of suppressing the immune system of a subject by administering a compound of formula (I).

摘要翻译： 通式（I）的化合物或其药学上可接受的前药，盐，水合物，溶剂合物，结晶形式或非对映异构体，其中A表示多种六元含氮杂环，Q为键，卤素， 1-4烷基，O，S，SO 2，CO或CS和X 1，X 2，X _{3和X 4任选被9个特定取代基取代，或者可以是氮。 还提供了包含载体和至少一种式（I）化合物的组合物。 还提供了通过施用式（I）化合物和通过施用式（I）化合物来抑制受试者的免疫系统的方法来治疗酪氨酸激酶相关疾病状态的方法。}

公开(公告)号：US20080142909A1

公开(公告)日：2008-06-19

申请号：US11930673

申请日：2007-10-31

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

摘要： The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

摘要翻译： 功率器件的蜂窝结构包括具有高掺杂漏极区的衬底。 在衬底上有相同掺杂的更轻掺杂的外延层。 外延层上方是由相反型掺杂形成的阱区。 覆盖阱是重掺杂的第一导电类型的上源层。 沟槽结构包括侧壁氧化物或覆盖沟槽侧壁的其它合适的绝缘材料。 沟槽的底部填充有掺杂多晶硅屏蔽层。 诸如氮化硅的层间电介质覆盖屏蔽。 栅极区域由另一层掺杂多晶硅形成。 第二层间电介质（通常为硼磷硅玻璃（BPSG））覆盖栅极。 在工作中，当适当的电压施加到栅极时，电流通过阱中的沟道在源极和漏极之间垂直流动。

公开(公告)号：US20070040214A1

公开(公告)日：2007-02-22

申请号：US11502594

申请日：2006-08-10

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/749

摘要： The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

摘要翻译： 功率器件的蜂窝结构包括具有高掺杂漏极区的衬底。 在衬底上有相同掺杂的更轻掺杂的外延层。 外延层上方是由相反型掺杂形成的阱区。 覆盖阱是重掺杂的第一导电类型的上源层。 沟槽结构包括侧壁氧化物或覆盖沟槽侧壁的其它合适的绝缘材料。 沟槽的底部填充有掺杂多晶硅屏蔽层。 诸如氮化硅的层间电介质覆盖屏蔽。 栅极区域由另一层掺杂多晶硅形成。 第二层间电介质（通常为硼磷硅玻璃（BPSG））覆盖栅极。 在工作中，当适当的电压施加到栅极时，电流通过阱中的沟道在源极和漏极之间垂直流动。

公开(公告)号：US20060270132A1

公开(公告)日：2006-11-30

申请号：US11194847

申请日：2005-08-01

申请人： Jun Zeng ,  Po-I Sun

发明人： Jun Zeng ,  Po-I Sun

IPC分类号： H01L21/337

CPC分类号： H01L29/8083 ,  H01L29/1066

摘要： A manufacturing process and a power junction field-effect transistor (JFET) are provided. The basic concept of the present invention is to allow the current to flow vertically from the drain region on the bottom side to the source region on the topside of the device. By regulating the voltage applied between the gate regions and the source region, the power junction field-effect transistor (JFET) of the present invention can be built to handle large current and higher voltage for power management purposes, as is similar to the metal oxide semiconductor field effect transistor (MOSFET).

公开(公告)号：US20060237782A1

公开(公告)日：2006-10-26

申请号：US11194353

申请日：2005-08-01

申请人： Jun Zeng ,  Po-I Sun

发明人： Jun Zeng ,  Po-I Sun

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0869 ,  H01L29/1095

摘要： A power semiconductor device includes a substrate, a well region, a body region, a trench gate, a gate oxide layer, an L-shaped source region, an inter-layer dielectric layer and a metal layer. The body region is formed on the well region. The trench gate is formed at bilateral sides of the well region. The gate oxide layer is formed on sidewall and bottom of the trench gate. The L-shaped source region has a horizontal portion and a vertical portion formed on a portion of top region and bilateral sides of the body region, respectively. The inter-layer dielectric layer is formed on the trench gate and a portion of the L-shaped source region, thereby defining a contact window therein. The metal layer is formed on the inter-layer dielectric layer, the body region and the L-shaped source region, and connected to the L-shaped source region via the contact window.

摘要翻译： 功率半导体器件包括衬底，阱区，体区，沟槽栅，栅极氧化层，L形源极区，层间电介质层和金属层。 身体区域形成在井区域上。 沟槽门形成在井区的双侧。 栅极氧化层形成在沟槽栅极的侧壁和底部。 L形源区域具有分别形成在身体区域的顶部区域和双侧的一部分上的水平部分和垂直部分。 层间电介质层形成在沟槽栅极和L形源极区域的一部分上，由此在其中限定接触窗口。 金属层形成在层间电介质层，主体区域和L形源极区域上，并且经由接触窗口连接到L形源极区域。

公开(公告)号：US07098108B1

公开(公告)日：2006-08-29

申请号：US09551187

申请日：2000-04-17

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L23/4827 ,  H01L24/32 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66333 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor device includes at least one device active region formed in a first surface of a semiconductor substrate, an electrical contact layer on a second surface of the semiconductor substrate, and at least one resistivity-lowering body positioned in a corresponding recess in the substrate and connected to the electrical contact layer. The body preferably comprises a material having an electrical resistivity lower than an electrical resistivity of the semiconductor substrate to thereby lower an effective electrical resistivity of the substrate. The device active region may be an active region of a power control device, such as a MOSFET or IGBT, for example. The body may preferably comprise an electrical conductor such as copper, aluminum, silver, solder, or doped polysilicon. The at least one recess and associated resistivity-lowering body preferably defines a proportion of the semiconductor substrate area adjacent the device active region greater than about 0.4 percent, and may extend into the semiconductor substrate a distance greater than about 25 percent of a thickness of the substrate.

公开(公告)号：US06946348B2

公开(公告)日：2005-09-20

申请号：US10795723

申请日：2004-03-05

申请人： Jun Zeng

发明人： Jun Zeng

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.

摘要翻译： 通过沟槽底部的掺杂剂注入将低功率沟槽MOSFET器件中的漂移区域合并在一起可以使用非常小的单元间距，导致非常高的沟道密度和均匀掺杂的沟道，从而显着降低 渠道阻力。 通过适当选择植入剂量和漂移区域的退火参数，可以严密控制器件的沟道长度，并且可以使沟道掺杂高度均匀。 与常规器件相比，阈值电压降低，沟道电阻降低，并且漂移区导通电阻也降低。 实现合并的漂移区域需要并入新的边缘终端设计，使得由P外延层和N + +衬底形成的PN结可以在晶片的边缘端接。