公开(公告)号：US08492794B2

公开(公告)日：2013-07-23

申请号：US13048366

申请日：2011-03-15

申请人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Kevin K. Chan ,  Wilfried E. Haensch ,  Tak H. Ning

IPC分类号： H01L29/66

CPC分类号： H01L29/737 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7375

摘要： A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

公开(公告)号：US08486797B1

公开(公告)日：2013-07-16

申请号：US13481048

申请日：2012-05-25

申请人： Bahman Hekmatshoartabari ,  Tak H. Ning ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoartabari ,  Tak H. Ning ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/44

CPC分类号： H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/7378

摘要： Bipolar junction transistors are provided in which at least one of an emitter contact, a base contact, or a collector contact thereof is formed by epitaxially growing a doped SixGe1-x layer, wherein x is 0≦x≦1, at a temperature of less than 500° C. The doped SixGe1-x layer comprises crystalline portions located on exposed surfaces of a crystalline semiconductor substrate and non-crystalline portions that are located on exposed surfaces of a passivation layer which can be formed and patterned on the crystalline semiconductor substrate. The doped SixGe1-x layer of the present disclosure, including the non-crystalline and crystalline portions, contains from 5 atomic percent to 40 atomic percent hydrogen.

摘要翻译： 提供了双极结晶体管，其中通过在较低温度下外延生长掺杂的SixGe1-x层（其中x为0 @ x @）来形成发射极接触，基极接触或集电极接触中的至少一个 掺杂的SixGe1-x层包括位于结晶半导体衬底的暴露表面上的结晶部分和位于可在晶体半导体衬底上形成和图案化的钝化层的暴露表面上的非晶体部分。 本公开的掺杂的SixGe1-x层包括非晶态和结晶部分，含有5原子％至40原子％的氢。

公开(公告)号：US20120295439A1

公开(公告)日：2012-11-22

申请号：US13564181

申请日：2012-08-01

申请人： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

发明人： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518

摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

摘要翻译： 在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层， 第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

公开(公告)号：US20120199806A1

公开(公告)日：2012-08-09

申请号：US13449378

申请日：2012-04-18

申请人： Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

发明人： Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

IPC分类号： H01L47/00

CPC分类号： H01L45/148 ,  H01L27/0623 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.

摘要翻译： 具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。 存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。 此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。 在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。 间隔层包含在绝缘区域内。

公开(公告)号：US20120139009A1

公开(公告)日：2012-06-07

申请号：US12958647

申请日：2010-12-02

申请人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

发明人： Tak H. Ning ,  Kevin K. Chan ,  Marwan H. Khater

IPC分类号： H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/7317 ,  H01L27/0821 ,  H01L27/1203 ,  H01L29/0808 ,  H01L29/165 ,  H01L29/66265

摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

摘要翻译： 在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。 因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。 基底还可以包括上硅基区和/或下硅基区。 在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。 此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

公开(公告)号：US08120095B2

公开(公告)日：2012-02-21

申请号：US11955940

申请日：2007-12-13

申请人： Herbert L. Ho ,  Jack A. Mandelman ,  Tak H. Ning ,  Yoichi Otani

发明人： Herbert L. Ho ,  Jack A. Mandelman ,  Tak H. Ning ,  Yoichi Otani

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L27/11565 ,  H01L27/1157

摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

摘要翻译： 本发明提供了具有可随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元，以及包括体现在机器可读介质中的半导体存储器件的设计结构。 在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于具有1至2μm的沟槽深度的沟槽结构，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

公开(公告)号：US20110241116A1

公开(公告)日：2011-10-06

申请号：US12754881

申请日：2010-04-06

申请人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

发明人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/265 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7839

摘要： A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer.

摘要翻译： 一种用于形成场效应晶体管（FET）的方法包括在硅层上形成栅叠层，所述栅叠层在栅极氧化层的顶部包括栅极多晶硅; 从栅极多晶硅形成完全硅化的栅极，并在硅层中形成源极/漏极硅化物区域; 用掺杂剂注入栅极硅化物和源极/漏极硅化物; 并且执行快速热退火以在栅极硅化物和栅极氧化物层之间形成栅极界面层，以及源极/漏极硅化物区域和硅层之间的源极/漏极界面层。

公开(公告)号：US20110102042A1

公开(公告)日：2011-05-05

申请号：US12987106

申请日：2011-01-08

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US07816728B2

公开(公告)日：2010-10-19

申请号：US10907686

申请日：2005-04-12

申请人： Herbert L. Ho ,  Jack A. Mandelman ,  Tak H. Ning ,  Yoichi Otani

发明人： Herbert L. Ho ,  Jack A. Mandelman ,  Tak H. Ning ,  Yoichi Otani

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

摘要翻译： 本发明提供具有随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。 在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于沟槽深度为1至2μm的沟槽结构内，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

公开(公告)号：US20100237389A1

公开(公告)日：2010-09-23

申请号：US12408205

申请日：2009-03-20

申请人： Mark C. HAKEY ,  Tak H. Ning ,  Philip J. Oldiges ,  Henry H.K. Tang

发明人： Mark C. HAKEY ,  Tak H. Ning ,  Philip J. Oldiges ,  Henry H.K. Tang

IPC分类号： H01L29/772 ,  H01L21/8232 ,  G06F17/50

CPC分类号： H01L21/84 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/12 ,  H01L29/78

摘要： The invention relates to a design structure, and more particularly, to a design structure for a heavy ion tolerant device, method of manufacturing the same and a structure thereof. The structure includes a first device having a diffusion comprising a drain region and source region and a second device having a diffusion comprising a drain region and source region. The first and second device are aligned in an end-to-end layout along a width of the diffusion of the first device and the second device. A first isolation region separating the diffusion of the first device and the second device.

摘要翻译： 本发明涉及一种设计结构，更具体地，涉及一种用于重离子容错装置的设计结构，其制造方法及其结构。 该结构包括具有包括漏极区域和源极区域的扩散的第一器件和具有包括漏极区域和源极区域的扩散部分的第二器件。 第一和第二装置沿着第一装置和第二装置的扩散的宽度在端对端布局中对准。 分离第一装置和第二装置的扩散的第一隔离区。