公开(公告)号：US20120299102A1

公开(公告)日：2012-11-29

申请号：US13569741

申请日：2012-08-08

申请人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

发明人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

IPC分类号： H01L29/786

CPC分类号： H01L29/66575 ,  H01L21/265 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7839

摘要： A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.

摘要翻译： 场效应晶体管（FET）包括位于硅层中的源极/漏极硅化物区域; 位于源/漏硅化物区域和硅层之间的源极/漏极界面层; 以及包括位于硅层上的栅极氧化物层，位于栅极氧化物层上的栅极界面层和位于栅极界面层上的栅极硅化物的完全硅化栅极堆叠。

公开(公告)号：US20110241116A1

公开(公告)日：2011-10-06

申请号：US12754881

申请日：2010-04-06

申请人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

发明人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/265 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7839

摘要： A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer.

摘要翻译： 一种用于形成场效应晶体管（FET）的方法包括在硅层上形成栅叠层，所述栅叠层在栅极氧化层的顶部包括栅极多晶硅; 从栅极多晶硅形成完全硅化的栅极，并在硅层中形成源极/漏极硅化物区域; 用掺杂剂注入栅极硅化物和源极/漏极硅化物; 并且执行快速热退火以在栅极硅化物和栅极氧化物层之间形成栅极界面层，以及源极/漏极硅化物区域和硅层之间的源极/漏极界面层。

公开(公告)号：US08664721B2

公开(公告)日：2014-03-04

申请号：US13569741

申请日：2012-08-08

申请人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhen Zhang

发明人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhen Zhang

IPC分类号： H01L27/12 ,  H01L29/45

CPC分类号： H01L29/66575 ,  H01L21/265 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7839

摘要： A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.

摘要翻译： 场效应晶体管（FET）包括位于硅层中的源极/漏极硅化物区域; 位于源/漏硅化物区域和硅层之间的源极/漏极界面层; 以及包括位于硅层上的栅极氧化物层，位于栅极氧化物层上的栅极界面层和位于栅极界面层上的栅极硅化物的完全硅化栅极堆叠。

公开(公告)号：US20110241115A1

公开(公告)日：2011-10-06

申请号：US12754079

申请日：2010-04-05

申请人： Christian Lavoie ,  Siegfried L. Maurer ,  Qiqing Ouyang ,  Paul Solomon ,  Zhen Zhang

发明人： Christian Lavoie ,  Siegfried L. Maurer ,  Qiqing Ouyang ,  Paul Solomon ,  Zhen Zhang

IPC分类号： H01L27/12 ,  H01L21/762 ,  H01L21/28

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/47 ,  H01L29/4908 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78654

摘要： A Schottky field effect transistor (FET) includes a gate stack located on a silicon on insulator (SOI) layer, the gate stack comprising a gate silicide region; and source/drain silicide regions located in the SOI layer, the source/drain silicide regions comprising and at least one of sulfur and fluorine, wherein an interface comprising arsenic is located between each of the source/drain silicide regions and the SOI layer. A method of forming a contact, the contact comprising a silicide region adjacent to a silicon region, includes co-implanting the silicide region with arsenic and at least one of sulfur and fluorine; and drive-in annealing the co-implanted silicide region to diffuse the arsenic to an interface between the silicide region and the silicon region.

摘要翻译： 肖特基场效应晶体管（FET）包括位于绝缘体上硅（SOI）层上的栅极堆叠，栅极叠层包括栅极硅化物区域; 位于SOI层中的源极/漏极硅化物区域，源极/漏极硅化物区域包括硫和氟中的至少一个，其中包含砷的界面位于每个源/漏硅化物区域和SOI层之间。 一种形成接触的方法，包括与硅区相邻的硅化物区的接触包括将砷化硅区域与砷和硫和氟中的至少一种共同注入; 并且将共注入的硅化物区域驱入退火以将砷扩散到硅化物区域和硅区域之间的界面。

公开(公告)号：US06812533B2

公开(公告)日：2004-11-02

申请号：US10328694

申请日：2002-12-24

申请人： Jin Cai ,  Tak H. Ning ,  Qiqing Ouyang

发明人： Jin Cai ,  Tak H. Ning ,  Qiqing Ouyang

IPC分类号： H01L2976

CPC分类号： H01L29/66265 ,  H01L29/0821 ,  H01L29/7317

摘要： An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.

摘要翻译： 电子电路包括双极晶体管，其包括导电背电极，导电背电极之上的绝缘体层以及绝缘体层上的n型或p型材料的半导体层。 半导体层包括用作集电极的掺杂区域和与掺杂区域接壤的重掺杂区域，用作绝缘体层和集电极接触电极之间的穿透层。 通过向背电极施加偏置电压，在集电极的掺杂区域中与绝缘体相邻地吸引多数载流子堆积层。

公开(公告)号：US20110248343A1

公开(公告)日：2011-10-13

申请号：US12755720

申请日：2010-04-07

申请人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

发明人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66643 ,  H01L29/7839

摘要： A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer.

摘要翻译： 一种用于形成肖特基场效应晶体管（FET）的方法包括在硅衬底上形成栅极堆叠，所述栅叠层在栅极金属层的顶部包括栅极多晶硅; 在栅极多晶硅和硅衬底上沉积金属层; 使金属层，栅极多晶硅和硅衬底退火，使得金属层完全消耗栅极多晶硅以形成栅极硅化物，并与硅衬底的部分反应以在硅衬底中形成源极/漏极硅化物区域; 并且在金属层的一部分不与栅极多晶硅或硅衬底反应的情况下，去除金属层的未反应部分。

公开(公告)号：US20070158739A1

公开(公告)日：2007-07-12

申请号：US11327256

申请日：2006-01-06

申请人： Massimo Fischetti ,  Qiqing Ouyang

发明人： Massimo Fischetti ,  Qiqing Ouyang

IPC分类号： H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/045 ,  H01L29/7842 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.

摘要翻译： 提供了在迁移率增强方面形成在（110）衬底上的具有改进性能的半导体（例如，互补金属氧化物半导体（CMOS））结构。 根据本发明，本发明的结构包括与（110）衬底结合使用的单张力应力衬垫，压应力浅沟槽隔离（STI）区域或拉伸应力嵌入井中的至少一个 以改善nFET和pFET的载流子迁移率。 本发明还涉及一种提供这种结构的方法。

公开(公告)号：US07227205B2

公开(公告)日：2007-06-05

申请号：US10930404

申请日：2004-08-31

申请人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

发明人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

IPC分类号： H01L29/76

CPC分类号： H01L29/165 ,  H01L29/1054 ,  H01L29/24 ,  H01L29/7842 ,  H01L29/7843

摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

摘要翻译： 本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。 单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。 单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。 单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。 本发明还提供了用应变诱导隔离区增加双轴应变的方法。 本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

公开(公告)号：US20070001262A1

公开(公告)日：2007-01-04

申请号：US11173540

申请日：2005-07-01

申请人： Qiqing Ouyang ,  Kai Xiu

发明人： Qiqing Ouyang ,  Kai Xiu

IPC分类号： H01L27/082

CPC分类号： H01L21/84 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/1203

摘要： A bipolar transistor includes a collector located over a substrate; and a heat conductive path connecting the substrate to the collector. The heat conductive path is filled with a heat conductive material such as metal or polysilicon. In one embodiment the heat conductive path runs through the collector to extract heat from the collector and drain it to the substrate. In alternate embodiments, the transistor can be a vertical or a lateral device. According to another embodiment, an integrated circuit using BiCMOS technology comprises pnp and npn bipolar transistors with heat conduction from collector to substrate and possibly p-channel and n-channel MOSFETS. According to yet another embodiment, a method for making a transistor in an integrated network comprises steps of etching the heat conducting path through the collector and to the substrate and fill with heat conductive material to provide a heat drain for the transistor comprising the collector.

摘要翻译： 双极晶体管包括位于衬底上方的集电极; 以及将基板连接到集电体的导热路径。 导热路径填充有诸如金属或多晶硅的导热材料。 在一个实施例中，导热路径穿过收集器以从集电器提取热量并将其排出到基板。 在替代实施例中，晶体管可以是垂直或横向装置。 根据另一实施例，使用BiCMOS技术的集成电路包括具有从集电极到衬底以及可能的p沟道和n沟道MOSFET的热传导的pnp和npn双极晶体管。 根据另一个实施例，一种用于在集成网络中制造晶体管的方法包括以下步骤：蚀刻通过集电器和衬底的导热路径，并填充导热材料，以为包括集电器的晶体管提供散热。

公开(公告)号：US20050184360A1

公开(公告)日：2005-08-25

申请号：US10787002

申请日：2004-02-25

申请人： Herbert Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul Papworth ,  Christopher Sheraw ,  Michael Steigerwalt

发明人： Herbert Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul Papworth ,  Christopher Sheraw ,  Michael Steigerwalt

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H01L27/082 ,  H01L27/12 ,  H01L29/73 ,  H01L29/732

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。