公开(公告)号：US06232131B1

公开(公告)日：2001-05-15

申请号：US09103961

申请日：1998-06-24

申请人： Yoshihisa Nagano ,  Eiji Fujii ,  Yasuhiro Uemoto

发明人： Yoshihisa Nagano ,  Eiji Fujii ,  Yasuhiro Uemoto

IPC分类号： H01L218242

CPC分类号： H01L28/55

摘要： The method for manufacturing a semiconductor device of this invention comprises the steps: forming a first wiring layer on a semiconductor substrate on which a capacitor element with a capacitor dielectric film is formed, and the capacitor dielectric film is at least one film selected from the group consisting of a capacitor dielectric film with high dielectric constant and a ferroelectric film; conducting a first annealing to said semiconductor substrate; forming a second wiring layer on said first wiring layer; etching selectively the first wiring layer and the second wiring layer; and conducting a second annealing to the semiconductor substrate, so that the stress provided to the capacitor element can be reduced by annealing after forming each wiring layer, and thus, it can prevent the increase of leakage current and deterioration of dielectric breakdown voltage of the capacitor element having a capacitor dielectric film comprising a high capacitor dielectric film and a ferroelectric film.

摘要翻译： 本发明的半导体装置的制造方法包括以下步骤：在形成有电容器电介质膜的电容器元件的半导体基板上形成第一布线层，并且所述电容器电介质膜为选自所述第一布线层 由具有高介电常数的电容器电介质膜和铁电体膜组成; 对所述半导体衬底进行第一退火; 在所述第一布线层上形成第二布线层; 选择性地蚀刻第一布线层和第二布线层; 并且对半导体衬底进行第二次退火，从而可以在形成每个布线层之后通过退火来减小提供给电容器元件的应力，从而可以防止漏电流的增加和电容器的介质击穿电压的劣化 具有包括高电容电介质膜和铁电体膜的电容器电介质膜的元件。

公开(公告)号：USRE41625E1

公开(公告)日：2010-09-07

申请号：US10829476

申请日：2004-04-22

申请人： Yoshihisa Nagano ,  Yasuhiro Uemoto

发明人： Yoshihisa Nagano ,  Yasuhiro Uemoto

IPC分类号： H01L29/94

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

摘要翻译： 保护绝缘膜沉积在形成在半导体衬底上的第一和第二场效应晶体管上。 在保护绝缘膜上形成由电容器下电极构成的电容器，由绝缘金属氧化物膜构成的电容绝缘膜和电容器上电极。 形成在保护绝缘膜中的第一接触插塞提供电容器下电极和第一场效应晶体管的杂质扩散层之间的直接连接。 形成在保护绝缘膜中的第二接触插塞提供电容器上电极和第二场效应晶体管的杂质扩散层之间的直接连接。

公开(公告)号：US07781230B2

公开(公告)日：2010-08-24

申请号：US11683580

申请日：2007-03-08

申请人： Akihiro Odagawa ,  Yoshihisa Nagano

发明人： Akihiro Odagawa ,  Yoshihisa Nagano

IPC分类号： B23B9/00

CPC分类号： C23C28/048 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  C23C28/36 ,  G11C13/0007 ,  H01L27/101

摘要： An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and resistance change characteristics is provided. An electro-resistance element has two or more states in which electric resistance values between a pair of electrodes and is switchable from one of the two or more states into another by applying a predetermined voltage or current between the electrodes. The electro-resistance element includes a substrate and a multilayer structure disposed on the substrate, the multilayer structure includes an upper electrode, a lower electrode and an electro-resistance layer disposed between the electrodes, wherein the electro-resistance layer includes Fe2O3, and Fe3O4 contained in an amount of 0% to 20% of Fe2O3 in percent by weight, the lower electrode is made of an iron oxide having a different composition from the electro-resistance layer and containing Fe3O4, and the electro-resistance layer and the lower electrode make contact with each other.

摘要翻译： 提供了具有与常规元件不同的构造并且与半导体制造工艺和电阻变化特性的亲和性优异的电阻元件。 电阻元件具有两个或更多个状态，其中一对电极之间的电阻值可以通过在电极之间施加预定的电压或电流而从两个或更多个状态之一切换到另一个状态。 电阻元件包括基板和设置在基板上的多层结构，多层结构包括上电极，下电极和设置在电极之间的电阻层，其中电阻层包括Fe 2 O 3和Fe 3 O 4 含有0重量％至20重量％的Fe 2 O 3的量，下电极由具有与电阻层不同的组成并含有Fe 3 O 4的氧化铁制成，并且电阻层和下电极 互相接触。

公开(公告)号：US20070240995A1

公开(公告)日：2007-10-18

申请号：US11683580

申请日：2007-03-08

申请人： Akihiro ODAGAWA ,  Yoshihisa Nagano

发明人： Akihiro ODAGAWA ,  Yoshihisa Nagano

IPC分类号： B32B9/00 ,  C23C28/00 ,  B32B19/00

CPC分类号： C23C28/048 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  C23C28/36 ,  G11C13/0007 ,  H01L27/101

摘要： An electro-resistance element that has a different configuration from conventional elements and is excellent in both affinity with semiconductor manufacturing processes and resistance change characteristics is provided. An electro-resistance element has two or more states in which electric resistance values between a pair of electrodes and is switchable from one of the two or more states into another by applying a predetermined voltage or current between the electrodes. The electro-resistance element includes a substrate and a multilayer structure disposed on the substrate, the multilayer structure includes an upper electrode, a lower electrode and an electro-resistance layer disposed between the electrodes, wherein the electro-resistance layer includes Fe2O3, and Fe3O4 contained in an amount of 0% to 20% of Fe2O3 in percent by weight, the lower electrode is made of an iron oxide having a different composition from the electro-resistance layer and containing Fe3O4, and the electro-resistance layer and the lower electrode make contact with each other.

摘要翻译： 提供了具有与常规元件不同的构造并且与半导体制造工艺和电阻变化特性的亲和性优异的电阻元件。 电阻元件具有两个或更多个状态，其中一对电极之间的电阻值可以通过在电极之间施加预定的电压或电流而从两个或更多个状态之一切换到另一个状态。 电阻元件包括基板和布置在基板上的多层结构，该多层结构包括上电极，下电极和设置在电极之间的电阻层，其中电阻层包括Fe 2 <3 O 3，Fe 3 O 4含有0〜20％的Fe 2 O 3 下部电极由与电阻层不同的组成的氧化铁制成，并含有Fe 3 O 3， SUB> 4 <！ - SIPO - >电极层和下电极彼此接触。

公开(公告)号：US07015564B2

公开(公告)日：2006-03-21

申请号：US10916482

申请日：2004-08-12

申请人： Yoshihisa Nagano ,  Shinichiro Hayashi

发明人： Yoshihisa Nagano ,  Shinichiro Hayashi

IPC分类号： H01L29/00

CPC分类号： H01L28/55 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/90

摘要： A capacitive element includes a lower electrode having a three-dimensional shape, an upper electrode formed so as to be opposed to the lower electrode, and a capacitor insulating film formed between the lower and upper electrodes and made of a crystallized ferroelectric material. The thickness of the capacitor insulating film is set at 12.5 through 100 nm both inclusive.

摘要翻译： 电容元件包括具有三维形状的下电极，形成为与下电极相对的上电极，以及形成在下电极和上电极之间并由结晶铁电材料制成的电容器绝缘膜。 电容绝缘膜的厚度设定为12.5〜100nm。

公开(公告)号：US20050051829A1

公开(公告)日：2005-03-10

申请号：US10916645

申请日：2004-08-12

申请人： Satoru Goto ,  Yoshihisa Nagano

发明人： Satoru Goto ,  Yoshihisa Nagano

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L28/55 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82

摘要： A semiconductor device includes: an insulating underlying layer of which surface portion has a concave portion; a lower electrode formed on the underlying layer along the inner face of the concave portion; a capacitor insulating film formed on the lower electrode and made of a high-dielectric or a ferroelectric subjected to thermal treatment for crystallization; and an upper electrode formed on the capacitor insulating film. The lower electrode and the upper electrode are made of a material that generates tensile stress in the thermal treatment for the capacitor insulating film, and the upper end part of the side wall and the corner part at the bottom face of the concave portion of the underlying layer are rounded.

摘要翻译： 半导体器件包括：表面部分具有凹部的绝缘下层; 沿着所述凹部的内表面形成在所述下层上的下电极; 在下电极上形成的电容器绝缘膜，由用于结晶的热处理的高电介质或铁电体构成; 以及形成在电容器绝缘膜上的上电极。 下电极和上电极由在电容绝缘膜的热处理中产生拉伸应力的材料制成，并且侧壁的上端部和位于底部的凹部的底部的底面的角部 层是圆形的。

公开(公告)号：US06730951B2

公开(公告)日：2004-05-04

申请号：US10175804

申请日：2002-06-21

申请人： Yoshihisa Nagano ,  Eiji Fujii

发明人： Yoshihisa Nagano ,  Eiji Fujii

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： A capacitor includes: a lower electrode; a capacitor insulating film made of a metal oxide and formed on the lower electrode; an upper electrode formed on the capacitor insulating film; and a buried insulating film surrounding the lower electrode. The lower electrode includes a conductive barrier layer that prevents diffusion of oxygen, and an insulating barrier layer that prevents diffusion of hydrogen is formed so as to be in contact with at least a side surface of the conductive barrier layer in a side surface of the lower electrode.

摘要翻译： 电容器包括：下电极; 由金属氧化物制成的电容绝缘膜，形成在下电极上; 形成在所述电容绝缘膜上的上电极; 以及包围下电极的掩埋绝缘膜。 下电极包括防止氧的扩散的导电阻挡层，并且形成防止氢的扩散的绝缘阻挡层，以在下部电极的侧表面中与至少导电阻挡层的侧表面接触 电极。

公开(公告)号：US06573111B2

公开(公告)日：2003-06-03

申请号：US10177781

申请日：2002-06-20

申请人： Yoshihisa Nagano ,  Yasuhiro Uemoto ,  Yuji Judai ,  Masamichi Azuma ,  Eiji Fujii

发明人： Yoshihisa Nagano ,  Yasuhiro Uemoto ,  Yuji Judai ,  Masamichi Azuma ,  Eiji Fujii

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L21/76895 ,  H01L27/11507

摘要： A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive material other than titanium.