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    Nonvolatile semiconductor memory
    62.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US07269073B2

    公开(公告)日：2007-09-11

    申请号：US11417248

    申请日：2006-05-04

    申请人： Ken Takeuchi

    发明人： Ken Takeuchi

    IPC分类号： G11C16/06

    CPC分类号： G11C8/08 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483

    摘要： A system includes a nonvolatile semiconductor memory and an electronic device which includes the nonvolatile semiconductor memory. The nonvolatile semiconductor memory selects a first operation mode while the nonvolatile semiconductor memory is connected to a first capacitor having a first capacity, and the nonvolatile semiconductor memory selects a second operation mode while the nonvolatile semiconductor memory is connected to a second capacitor having a second capacity higher than a first capacity. The nonvolatile semiconductor memory operates in the selected one of the first and second operation modes. The first operation mode is a mode in which a peak of current consumption takes a first value, and a second operation mode is a mode in which a peak of current consumption takes a second value lower than the first value.

    摘要翻译： 一种系统包括非易失性半导体存储器和包括非易失性半导体存储器的电子器件。 非易失性半导体存储器选择第一操作模式，同时将非易失性半导体存储器连接到具有第一容量的第一电容器，并且非易失性半导体存储器选择第二操作模式，而非易失性半导体存储器连接到具有第二容量的第二电容器 高于第一容量。 非易失性半导体存储器以所选择的第一和第二操作模式操作。 第一操作模式是电流消耗的峰值取第一值，第二操作模式是电流消耗的峰值低于第一值的第二值的模式。

    Non-volatile semiconductor memory device
    63.
    发明授权
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07242616B2

    公开(公告)日：2007-07-10

    申请号：US11321865

    申请日：2005-12-30

    申请人： Ken Takeuchi

    发明人： Ken Takeuchi

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A non-volatile semiconductor memory device comprises a semiconductor substrate; a cell well formed in the semiconductor substrate; a first sub cell array including part of a cell array of NAND cells arranged in array in the cell well; a second sub cell array including the remainder of the cell array and arranged in the same cell well as that for the first sub cell array; a first sense amp corresponding to the first sub cell array; a second sense amp corresponding to the second sub cell array; a first bit line group including one of portions of a bit line group divided on the way extending from the first sense amp to the second sense amp and corresponding to the first sub cell array; and a second bit line group including the other of the portions of the bit line group divided on the way and corresponding to the second sub cell array.

    摘要翻译： 非易失性半导体存储器件包括半导体衬底; 在半导体衬底中形成的电池; 第一子单元阵列，其包括在单元阱中排列成阵列的NAND单元的单元阵列的一部分; 第二子单元阵列，其包括所述单元阵列的其余部分，并且排列在与所述第一子单元阵列相同的单元中; 对应于第一子单元阵列的第一感测放大器; 对应于第二子单元阵列的第二感测放大器; 第一位线组包括在从第一读出放大器延伸到第二读出放大器并且对应于第一子单元阵列的路径上划分的位线组的部分之一; 以及第二位线组，包括在路线上被划分并对应于第二子单元阵列的位线组中的另一部分。

    Semiconductor memory device
    66.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060203547A1

    公开(公告)日：2006-09-14

    申请号：US11319474

    申请日：2005-12-29

    申请人： Ken Takeuchi

    发明人： Ken Takeuchi

    IPC分类号： G11C16/06

    CPC分类号： G11C16/26 ,  G11C16/0483

    摘要： A semiconductor memory device includes: first and second cell arrays each having electrically rewritable and non-volatile semiconductor memory cells arranged therein, the first and second cell arrays being disposed in the direction of each bit line for transferring cell data and physically independent of each other; a sense amplifier disposed between the first and second cell arrays to be common to them; and a decode circuit configured to select a memory cell in the first and second cell arrays in accordance with address assigned to the first and second cell arrays in such a way that the first and second cell arrays serve as one memory plane in logic.

    摘要翻译： 一种半导体存储器件包括：第一和第二单元阵列，每个阵列具有布置在其中的电可重写和非易失性半导体存储单元，第一和第二单元阵列沿每个位线的方向设置，用于传送单元数据，并且在物理上彼此独立 ; 设置在所述第一和第二单元阵列之间的感测放大器以使它们共同; 以及解码电路，被配置为根据分配给第一和第二单元阵列的地址，以使得第一和第二单元阵列用作逻辑中的一个存储器平面的方式来选择第一和第二单元阵列中的存储单元。

    Non-volatile semiconductor memory
    67.
    发明申请
    Non-volatile semiconductor memory 失效

    公开(公告)号：US20050125595A1

    公开(公告)日：2005-06-09

    申请号：US11032165

    申请日：2005-01-11

    申请人： Ken Takeuchi ,  Tamio Ikehashi ,  Toshihiko Himeno

    发明人： Ken Takeuchi ,  Tamio Ikehashi ,  Toshihiko Himeno

    IPC分类号： G06F12/16 ,  G11C16/02 ,  G11C16/06 ,  G11C16/20 ,  G11C29/04 ,  G06F13/00

    CPC分类号： G11C16/20

    摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.

    Semiconductor integrated circuit
    70.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06674318B2

    公开(公告)日：2004-01-06

    申请号：US10231082

    申请日：2002-08-30

    申请人： Kazushige Kanda ,  Tamio Ikehashi ,  Ken Takeuchi ,  Kenichi Imamiya

    发明人： Kazushige Kanda ,  Tamio Ikehashi ,  Ken Takeuchi ,  Kenichi Imamiya

    IPC分类号： G05F110

    CPC分类号： G11C7/062

    摘要： A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit. In order to provide a voltage trimming function, a voltage intended to be set in an external terminal may be given from the outside to deactivate a feedback system of the limiter circuit to operate a resistance value of the limiter circuit to detect and store a limiter flag. Thus, there is provided a semiconductor integrated circuit capable of simply monitoring the output voltage state of an internal power supply circuit by the external terminal and easily trimming an internal voltage.

    摘要翻译： 半导体集成电路包括限幅电路，用于输出电压确定标志，以便将升压电路的升压电压设定为预定值;以及监视电路，用于监视限幅器电路的监视节点以输出监视信号 用于稳定第一外部端子的升压电压。 监控电路通过比较器检测在限制器电路的操作开始之后电压确定标志从“H”到“L”的第一电平变化，供给外部电源电压和外部参考电压 给出第二和第三外部端子，然后在限幅器电路的操作期间输出用于保持恒定逻辑电平的监视信号。 为了提供电压调整功能，可以从外部给出旨在设置在外部端子中的电压以去激活限幅器电路的反馈系统，以操作限幅器电路的电阻值以检测和存储限幅器标志 。 因此，提供了能够简单地通过外部端子监视内部电源电路的输出电压状态并容易地修整内部电压的半导体集成电路。