公开(公告)号：US07253094B1

公开(公告)日：2007-08-07

申请号：US10993031

申请日：2004-11-19

申请人： Jie Zhang ,  Vinay Krishna ,  Chan-Lon Yang

发明人： Jie Zhang ,  Vinay Krishna ,  Chan-Lon Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/02063 ,  H01L21/32134 ,  H01L21/76814

摘要： A method for processing a semiconductor topography which includes removing metal oxide layers from the bottom of contact openings is provided. In some embodiments, the method may include etching openings within a dielectric layer to expose conductive and silicon surfaces within the semiconductor topography is provided. In such cases, the method further includes exposing the semiconductor topography to an etch process adapted to remove metal oxide material from the conductive surfaces without substantially removing material from the silicon surfaces. In some cases, the etch chemistry used for the etch process may include sulfuric acid. In addition or alternatively, the etch chemistry may include hydrogen peroxide. In any case, the etch chemistry may be distinct from chemistries used to remove residual matter generated from the etch process used to form the openings within the dielectric and/or the removal of the masking layer used to pattern the openings.

摘要翻译： 提供一种处理半导体形貌的方法，其包括从接触孔的底部去除金属氧化物层。 在一些实施例中，该方法可以包括蚀刻介电层内的开口以暴露半导体形貌中的导电和硅表面。 在这种情况下，该方法还包括将半导体形貌暴露于适于从导电表面除去金属氧化物材料的蚀刻工艺，而基本上不从硅表面去除材料。 在一些情况下，用于蚀刻工艺的蚀刻化学可能包括硫酸。 另外或替代地，蚀刻化学品可以包括过氧化氢。 在任何情况下，蚀刻化学可能不同于用于去除由用于在电介质中形成开口的蚀刻工艺产生的残余物质和/或去除用于图案化开口的掩模层的化学物质。

公开(公告)号：US06492250B1

公开(公告)日：2002-12-10

申请号：US09638923

申请日：2000-08-15

申请人： Hidetake Horiuch ,  Chan-Lon Yang

发明人： Hidetake Horiuch ,  Chan-Lon Yang

IPC分类号： H01L214763

CPC分类号： H01L29/4933 ,  H01L21/28061

摘要： A polycide gate structure and a method of forming the polycide gate. A substrate having a gate dielectric layer, a polysilicon layer, a silicide layer and an insulation layer thereon is provided. The polysilicon layer is above the gate dielectric layer, the silicide layer is above the polysilicon layer, and the insulation layer is above the silicide layer. A patterned photoresist layer is formed over the insulation layer. Using the photoresist layer as a mask, an anisotropic etching operation is carried out to remove the exposed insulation layer. Again using the photoresist layer as a mask, a first type of plasma is used to carry out a first anisotropic etching operation to remove the exposed silicide layer. A metallic oxide layer is formed on the sidewalls of the silicide layer by the oxidation of a portion of the retained silicide layer. Using the photoresist layer as a mask, a second type of plasma is used to carry out a second anisotropic etching operation to remove the exposed polysilicon layer. The metallic oxide layer is resistant to attack by the second type of plasma.

摘要翻译： 多晶硅栅极结构和形成多晶硅栅极的方法。 提供了具有栅极电介质层，多晶硅层，硅化物层及其绝缘层的衬底。 多晶硅层位于栅极电介质层之上，硅化物层位于多晶硅层上方，绝缘层位于硅化物层之上。 在绝缘层上形成图案化的光致抗蚀剂层。 使用光致抗蚀剂层作为掩模，进行各向异性蚀刻操作以去除暴露的绝缘层。 再次使用光致抗蚀剂层作为掩模，使用第一类型的等离子体进行第一各向异性蚀刻操作以除去暴露的硅化物层。 通过一部分保留的硅化物层的氧化，在硅化物层的侧壁上形成金属氧化物层。 使用光致抗蚀剂层作为掩模，使用第二类型的等离子体进行第二种各向异性蚀刻操作以去除暴露的多晶硅层。 金属氧化物层耐受第二类型等离子体的侵蚀。

公开(公告)号：US06251791B1

公开(公告)日：2001-06-26

申请号：US09357246

申请日：1999-07-20

申请人： Ming-Huan Tsai ,  Chan-Lon Yang

发明人： Ming-Huan Tsai ,  Chan-Lon Yang

IPC分类号： H01L21311

CPC分类号： H01L21/31144 ,  H01L21/31116

摘要： A method for eliminating the etching microloading effect is proposed for the invention. Spirit of the invention is that a coating layer is formed on a photo-resist that covers a substrate before the substrate is etched, where coating layer maybe a polymer layer or a dielectric layer. Because step coverage of the coating layer is limited by the aspect of trench, for photo-resist it means the width of openings, it is indisputable that depth of coating layer on bottom of a narrow opening is smaller than depth of coating layer on bottom of a wide opening. Therefore, during following etching process, although etching microloading effect induces etching rate is higher in the wide opening and is lower in the narrow opening, but the thicker coating layer on bottom of the wide opening also requires larger etching time than the narrow opening. Consequently, it is crystal-clear that the etching microloading effect is cancelled and then depth of the wide trench is equal to depth of the narrow trench.

摘要翻译： 本发明提出了一种消除蚀刻微加载效应的方法。 本发明的精神是在蚀刻基板之前在覆盖基板的光致抗蚀剂上形成涂层，其中涂层可以是聚合物层或电介质层。 由于涂层的层间覆盖受到沟槽的限制，对于光刻胶而言，它意味着开口的宽度，不可否认，窄开口底部的涂层深度小于底部的涂层深度 一个广阔的开幕 因此，在随后的蚀刻过程中，虽然蚀刻微加载效应导致在宽开口中的蚀刻速率较高，而在窄开口中蚀刻速率较低，但是宽开口底部较厚的涂层也需要比窄开口更大的蚀刻时间。 因此，清楚的是蚀刻微加载效应被消除，然后宽沟槽的深度等于窄沟槽的深度。

公开(公告)号：US06218084B1

公开(公告)日：2001-04-17

申请号：US09212727

申请日：1998-12-15

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Michael W C Huang

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Michael W C Huang

IPC分类号： G03F742

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01L21/31116

摘要： A method described for removing a photoresist/polymers layer on a substrate. The method comprises the steps of providing a wafer having an oxide layer, a photoresist/polymers layer, an opening penetrating through the photoresist/polymers layer and the oxide layer, and the sidewall polymer on the surface of photoresist layer and the oxide layer. An in-situ plasma-etching step using an additional gas mixed with oxygen as source is performed to remove the photoresist/polymers layer without residues, no damages to substrate and oxide and no changes on the critical dimension of the opening during etching step.

公开(公告)号：US06184147B2

公开(公告)日：2001-02-06

申请号：US09263421

申请日：1999-03-05

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Keh-Ching Huang

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Keh-Ching Huang

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01J37/32082 ,  H01J2237/3347 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for forming a high aspect ration (HAR>4:1) borderless contact hole is described. The method forms a contact/via hole in the silicon oxide layer by performing an etching process with an etchant, C4F8/C2F6,/Ar/CO or C4F8/Ar/CO, on an etcher. The etcher includes a ring, a roof, a chiller and a chamber. The etchant used in the etching process is controlled under conditions including a C4F8 flow of about 10 to 20 sccm, a CO flow of about 1 to 100 sccm, and an Ar flow of about 100 to 500 sccm. The flow of C2F6 is about 0.5 to 1.5 times that of C4F8. The conditions of the etcher include a roof temperature of about 150 to 300° C., a chiller temperature of about −20 to 20° C., a wall temperature of about 150 to 400° C., a ring temperature of about 150 to 400° C., and a pressure within the chamber of about 4 to 50 mtorr. By controlling the chamber pressure and the deposition rate of the polymer molecules, a properly profiled contact hole is obtained.

摘要翻译： 描述了形成高纵横比（HAR> 4:1）无边界接触孔的方法。 该方法通过在蚀刻剂上用蚀刻剂C 4 F 8 / C 2 F 6，/ Ar / CO或C 4 F 8 / Ar / CO执行蚀刻处理来形成氧化硅层中的接触/通孔。 蚀刻器包括环，屋顶，冷却器和室。 在蚀刻工艺中使用的蚀刻剂在约10至20sccm的C 4 F 8流量，约1至100sccm的CO流量和约100至500sccm的Ar流量的条件下进行控制。 C2F6的流量约为C4F8的0.5〜1.5倍。 蚀刻器的条件包括约150至300℃的屋顶温度，约-20至20℃的冷却器温度，约150至400℃的壁温度，约150至400℃的环境温度 400℃，室内的压力为约4至50毫托。 通过控制室压力和聚合物分子的沉积速率，获得适当的异型接触孔。

公开(公告)号：US06184142B2

公开(公告)日：2001-02-06

申请号：US09302204

申请日：1999-04-26

申请人： Hsien-Ta Chung ,  Chan-Lon Yang ,  Tong-Yu Chen ,  Tri-Rung Yew

发明人： Hsien-Ta Chung ,  Chan-Lon Yang ,  Tong-Yu Chen ,  Tri-Rung Yew

IPC分类号： H01L2100

CPC分类号： H01L21/76807 ,  H01L21/31144 ,  H01L21/76802

摘要： A simplified method is disclosed for etching low k organic dielectric film. A substrate is provided with a hardmask layer and low k organic dielectric layer formed thereon in which hardmask layer is on the dielectric layer. A layer of photoresist is formed on the hardmask layer and imaged with a pattern by exposure through a dark field mask. As a key step, the pattern is transferred into the hardmask layer by dry etching and then the photoresist is stripped in-situ. Then, the interconnect is formed by using dry etching the low k organic dielectric layer using the hardmask layer as a mask, and readying it for the next semiconductor process.

摘要翻译： 公开了一种用于蚀刻低k有机介电膜的简化方法。 衬底上设置有硬掩模层和形成在其上的低k有机介电层，其中硬掩模层位于电介质层上。 在硬掩模层上形成光致抗蚀剂层，并通过暗场掩模曝光以图案成像。 作为关键步骤，通过干蚀刻将图案转移到硬掩模层中，然后原位剥离光致抗蚀剂。 然后，通过使用硬掩模层作为掩模使用干式蚀刻低k有机介电层形成互连，并将其准备用于下一个半导体工艺。

公开(公告)号：US06180532B2

公开(公告)日：2001-01-30

申请号：US09213129

申请日：1998-12-15

申请人： Chan-Lon Yang ,  Tong-Yu Chen ,  Tsu-An Lin

发明人： Chan-Lon Yang ,  Tong-Yu Chen ,  Tsu-An Lin

IPC分类号： H01L213065

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144

摘要： A method for forming a contact hole in a silicon oxide layer formed over a silicon nitride layer and a substrate performs an etching process with an etchant, C4F8/Ar or C4F8/C2F6/Ar, on an inductively coupled plasma etcher. The inductively coupled plasma etcher contains a chamber, a ring, and a roof. The etchant used in the etching process is controlled by conditions that include a C4F8 flow of about 10 to 20 sccm, a CO flow of less than about 100 sccm, and an Ar flow of about 50 to 500 sccm. In the meantime, the conditions of the inductively coupled plasma etcher include a roof temperature of about 150 to 300 ° C., a ring temperature of about 150 to 400 ° C., and a pressure within the chamber of about 4 to 50 mtorr. By performing a plasma etching process under the foregoing conditions, a properly profiled contact hole is obtained.

摘要翻译： 在形成在氮化硅层和基板上的氧化硅层中形成接触孔的方法在电感耦合等离子体蚀刻器上用蚀刻剂C4F8 / Ar或C4F8 / C2F6 / Ar进行蚀刻处理。 电感耦合等离子体蚀刻器包含一个室，一个环和一个屋顶。 在蚀刻工艺中使用的蚀刻剂由包括约10至20sccm的C 4 F 8流量，小于约100sccm的CO流量和约50至500sccm的Ar流量的条件控制。 同时，电感耦合等离子体蚀刻器的条件包括约150-300℃的屋顶温度，约150-400℃的环境温度和室内压力为约4-50mtorr。 通过在上述条件下进行等离子体蚀刻工艺，可以获得适当的异型接触孔。

公开(公告)号：US6147007A

公开(公告)日：2000-11-14

申请号：US330597

申请日：1999-06-11

申请人： Chan-Lon Yang ,  Wei-Che Huang ,  Tong-Yu Chen

发明人： Chan-Lon Yang ,  Wei-Che Huang ,  Tong-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814

摘要： The present invention relates to a method of forming a contact hole on the semiconductor wafer. The semiconductor wafer comprises, in ascending order, a substrate, a silicon nitride layer, a silicon oxide layer, and a photo-resist layer. There is a hole in the photo-resist layer. The method comprises: (1) performing a first anisotropic etching process in a downward direction to remove the silicon oxide layer under the hole down to the surface of the silicon nitride layer to form a recess; (2) performing an in-situ plasma cleaning process to entirely remove the polymer material remaining at the bottom of the recess; (3) performing an in-situ second anisotropic etching process in a downward direction to remove the silicon nitride layer from the bottom of the recess down to the surface of the substrate to form the contact hole; (4) performing another in-situ cleaning process to entirely remove the polymer material remaining at the bottom of the contact hole.

摘要翻译： 本发明涉及在半导体晶片上形成接触孔的方法。 半导体晶片按照升序包括衬底，氮化硅层，氧化硅层和光致抗蚀剂层。 光致抗蚀剂层中有一个孔。 该方法包括：（1）沿向下的方向进行第一各向异性蚀刻处理，以将氧化硅层下面的氮化硅层的表面去除，形成凹部; （2）进行原位等离子体清洗工艺以完全除去残留在凹部底部的聚合物材料; （3）在向下的方向上进行原位第二各向异性蚀刻工艺，以将氮化硅层从凹槽的底部向下移动到衬底的表面，以形成接触孔; （4）进行另一原位清洗处理以完全除去留在接触孔底部的聚合物材料。

公开(公告)号：US08980753B2

公开(公告)日：2015-03-17

申请号：US12886580

申请日：2010-09-21

申请人： Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

发明人： Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

IPC分类号： H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L21/823814

摘要： A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.

摘要翻译： 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

公开(公告)号：US08765588B2

公开(公告)日：2014-07-01

申请号：US13248011

申请日：2011-09-28

申请人： Pong-Wey Huang ,  Chan-Lon Yang ,  Chang-Hung Kung ,  Wei-Hsin Liu ,  Ya-Hsueh Hsieh ,  Bor-Shyang Liao ,  Teng-Chun Hsuan ,  Chun-Yao Yang

发明人： Pong-Wey Huang ,  Chan-Lon Yang ,  Chang-Hung Kung ,  Wei-Hsin Liu ,  Ya-Hsueh Hsieh ,  Bor-Shyang Liao ,  Teng-Chun Hsuan ,  Chun-Yao Yang

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545

摘要： A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.

摘要翻译： 半导体工艺包括以下步骤。 介电层形成在基板上，并且介电层具有第一凹槽和第二凹槽。 形成金属层以覆盖介电层的表面，第一凹部和第二凹部。 部分地将牺牲的材料填充到第一凹部和第二凹部中，使得每个凹部中的金属层的一部分分别被覆盖。 去除每个凹部中的未覆盖的金属层。 牺牲的材料被去除。 执行蚀刻处理以去除第一凹部中的剩余金属层并且将剩余的金属层保留在第二凹部中。