公开(公告)号：US08581330B2

公开(公告)日：2013-11-12

申请号：US13326972

申请日：2011-12-15

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar.

摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱和多个存储单元。 层叠体包括设置在栅电极之间的多个层叠栅电极和电极间绝缘层。 半导体柱穿过堆叠体。 多个存储单元沿层叠方向设置。 存储单元包括通过气隙设置在半导体柱和栅电极之间的电荷陷阱层。 块绝缘层设置在电荷陷阱层和栅电极之间。 多个存储单元中的每一个设置有被配置为保持电荷陷阱层和半导体柱之间的气隙距离的支撑部分。

公开(公告)号：US08119020B2

公开(公告)日：2012-02-21

申请号：US11826922

申请日：2007-07-19

申请人： Shoko Ito ,  Makiko Katano ,  Atsuko Kawasaki ,  Masahiro Kiyotoshi

发明人： Shoko Ito ,  Makiko Katano ,  Atsuko Kawasaki ,  Masahiro Kiyotoshi

IPC分类号： B44C1/22

CPC分类号： H01L21/67393 ,  H01L21/67253 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11521 ,  Y10S414/135

摘要： A method for manufacturing an electronic device using a closed-type transport container, includes: controlling relative humidity inside the closed-type transport container to be lower than ambient relative humidity outside the closed-type transport container on a particular interprocess transport path in which an intermediate product stored in the closed-type transport container is transported from a first manufacturing process to a second manufacturing process. The first manufacturing process allows basic compounds containing nitrogen atoms to be released from the intermediate product. The second manufacturing process is susceptible to degradation due to contamination by the basic compounds.

摘要翻译： 一种使用封闭式输送容器的电子装置的制造方法，其特征在于，包括：在所述封闭式输送容器内部的相对湿度比所述封闭式输送容器外的环境相对湿度低的特定过程输送路径， 存储在封闭式运输容器中的中间产品从第一制造过程运输到第二制造过程。 第一制造方法允许含有氮原子的碱性化合物从中间产物中释放出来。 第二制造过程由于碱性化合物的污染而易于降解。

公开(公告)号：US08017989B2

公开(公告)日：2011-09-13

申请号：US12659703

申请日：2010-03-17

申请人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi

发明人： Yoshio Ozawa ,  Ichiro Mizushima ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.

摘要翻译： 一种非易失性半导体存储器件，包括具有半导体层和设置在其表面上的绝缘材料的半导体衬底，绝缘材料的表面被半导体层覆盖，并且设置在半导体层上的多个存储单元，存储器 电池包括通过覆盖半导体层的表面而提供的第一电介质膜，设置在绝缘材料上方和第一电介质膜上的多个电荷存储层，设置在每个电荷存储层上的多个第二电介质膜，多个 设置在每个第二电介质膜上的导电层，以及杂质扩散层，其部分或整体形成在绝缘材料的至少上方和半导体层的内部，并且其底端的至少一部分由绝缘体的上表面 材料。

公开(公告)号：US08008732B2

公开(公告)日：2011-08-30

申请号：US11858731

申请日：2007-09-20

申请人： Masahiro Kiyotoshi ,  Akihito Yamamoto ,  Yoshio Ozawa ,  Fumitaka Arai ,  Riichiro Shirota

发明人： Masahiro Kiyotoshi ,  Akihito Yamamoto ,  Yoshio Ozawa ,  Fumitaka Arai ,  Riichiro Shirota

IPC分类号： H01L27/115

CPC分类号： H01L27/249 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28282 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L29/513 ,  H01L29/518 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1633

摘要： A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

摘要翻译： 半导体存储器包括通过在垂直于衬底的方向上堆叠平行于衬底延伸的多个层而形成的多个条状有源区域，形成在有源区域的第一侧表面上的第一栅极电极，第一栅极电极 侧表面垂直于衬底，形成在有源区的第二侧表面上的第二栅电极，第二侧表面垂直于衬底。 这些层彼此自对准地构图，有源区和第一栅电极的交点形成多个存储单元，并且交叉平面中的多个存储单元共享第一栅电极。

公开(公告)号：US20110156132A1

公开(公告)日：2011-06-30

申请号：US12784032

申请日：2010-05-20

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device according to an embodiment includes memory strings which have a plurality of transistors including gate electrode films formed over sides of columnar semiconductor films on gate dielectric films in a height direction of the semiconductor films, and which are arranged in a matrix shape substantially perpendicularly above a substrate. The gate electrode films of the transistors at same height of the memory strings arranged in a first direction are connected to one another. A distance between the semiconductor films at least in a forming position of the transistor at an uppermost layer of the memory strings adjacent to each other in the first direction is smaller than double of thickness of the gate dielectric films.

摘要翻译： 根据实施例的非易失性半导体存储器件包括具有多个晶体管的存储器串，所述多个晶体管包括形成在半导体膜的高度方向上的栅极电介质膜上的柱状半导体膜的侧面上的栅电极膜，并且以矩阵形状 基本上垂直于基底上方。 在沿第一方向布置的存储器串的相同高度处的晶体管的栅极电极膜彼此连接。 在第一方向上彼此相邻的存储器串的最上层的晶体管的至少形成位置的半导体膜之间的距离小于栅极电介质膜的厚度的两倍。

公开(公告)号：US20090283739A1

公开(公告)日：2009-11-19

申请号：US12408598

申请日：2009-03-20

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L29/786 ,  H01L21/28

CPC分类号： H01L27/1021 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/24

摘要： There is provided a nonvolatile storage device including a plurality of component memory layers. The plurality of component memory layers are stacked In a direction perpendicular to a layer surface. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring and a stacked structure unit provided between the first wiring and the second wiring and including a recording layer. At least one of the first wiring and the second wiring includes a protruding portion provided on a portion opposed to the recording layer and protruding toward the recording layer side.

摘要翻译： 提供了包括多个部件存储层的非易失性存储装置。 多个分量存储层在垂直于层表面的方向上堆叠。 多个分量存储层中的每一个包括第一布线，与第一布线不平行的第二布线和设置在第一布线和第二布线之间并包括记录层的堆叠结构单元。 第一布线和第二布线中的至少一个包括设置在与记录层相对的部分上且朝向记录层侧突出的突出部分。

公开(公告)号：US20090283737A1

公开(公告)日：2009-11-19

申请号：US12408510

申请日：2009-03-20

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L47/00 ,  H01L21/336

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/105 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings. The plurality of layer selection transistors are connected to at least one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, and collectively selects the at least one in the same plane.

摘要翻译： 提供具有多个单位存储层的非易失性存储装置和多个层选择晶体管。 多个单元存储层在垂直于单元存储层的层表面的方向上层叠。 每个单元存储层包括多个第一布线，多个第二布线，其设置成不平行于多个第一布线，以及记录层，设置在多个第一布线和多个第二布线之间。 多个层选择晶体管连接到每个单元存储层的多个第一布线和多个第二布线中的至少一个，并且在同一平面中共同选择至少一个。

公开(公告)号：US20090212352A1

公开(公告)日：2009-08-27

申请号：US12391953

申请日：2009-02-24

申请人： Kenji AOYAMA ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

发明人： Kenji AOYAMA ,  Eiji Ito ,  Masahiro Kiyotoshi ,  Tadashi Iguchi ,  Moto Yabuki

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/764 ,  H01L29/66825

摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity.

摘要翻译： 半导体存储器件具有半导体衬底，在半导体衬底上以预定间隔形成的多个字线，每个字线具有栅极绝缘膜，电荷存储层，第一绝缘膜和控制栅电极，它们被堆叠 并且包括位于栅极绝缘膜的高度之上的金属氧化物层，覆盖字线的一侧的第二绝缘膜和字线之间的半导体衬底的表面，并且具有15nm的膜厚度或 并且形成在彼此相邻的字线之间的第三绝缘膜，使得低于金属氧化物层的电平的区域具有空腔。

公开(公告)号：US20090011570A1

公开(公告)日：2009-01-08

申请号：US12146143

申请日：2008-06-25

申请人： Ichiro Mizushima ,  Yoshio Ozawa ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi ,  Minako Inukai ,  Kaori Umezawa ,  Hiroaki Yamada

发明人： Ichiro Mizushima ,  Yoshio Ozawa ,  Takashi Nakao ,  Akihito Yamamoto ,  Takashi Suzuki ,  Masahiro Kiyotoshi ,  Minako Inukai ,  Kaori Umezawa ,  Hiroaki Yamada

IPC分类号： H01L21/76

CPC分类号： H01L21/764

摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层 在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层 从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。

公开(公告)号：US07416987B2

公开(公告)日：2008-08-26

申请号：US11472282

申请日：2006-06-22

申请人： Katsuhiko Hieda ,  Masahiro Kiyotoshi

发明人： Katsuhiko Hieda ,  Masahiro Kiyotoshi

IPC分类号： H01L21/311

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/76229

摘要： According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.

摘要翻译： 根据本发明，提供了一种半导体器件制造方法，其具有在半导体衬底的表面部分中形成掩模材料，并且通过使用掩模材料形成具有突起的台阶; 在所述半导体衬底上形成电介质膜，以填充所述台阶并使整个表面平坦化; 电介质膜退火; 蚀刻介电膜，使得电介质膜的表面位于掩模材料的上表面和下表面之间; 以及去除所述掩模材料以暴露所述半导体衬底的所述突起的表面。