公开(公告)号：US6077574A

公开(公告)日：2000-06-20

申请号：US912468

申请日：1997-08-18

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L21/768 ,  C23C16/40 ,  C23C16/507 ,  C23C16/511 ,  H01L21/314 ,  H01L21/316 ,  H01L23/522 ,  H05H1/24

CPC分类号： H01L21/02274 ,  C23C16/401 ,  C23C16/507 ,  C23C16/511 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/31625

摘要： In a process for forming a plasma CVD fluorine-doped SiO.sub.2 dielectric film, a feed gas to be supplied to a plasma CVD apparatus is composed to include not only SiH.sub.4 gas, O.sub.2 gas, CF.sub.4 gas and Ar gas but also CO.sub.2 gas, and the amount of carbon and the amount of fluorine included in the feed gas are controlled independently of each other, to form a plasma CVD silicon-based SiO.sub.2 dielectric film doped with fluorine in the concentration range of 4.0.times.10.sup.21 atoms/cc to 1.0.times.10.sup.22 atoms/cc, and carbon in the concentration range of 3.0.times.10.sup.19 atoms/cc to 1.0.times.10.sup.21 atoms/cc. Thus, a plasma CVD silicon-based SiO.sub.2 dielectric film having a low dielectric constant and a sufficient "resistance to moisture" is obtained.

摘要翻译： 在形成等离子体CVD氟掺杂的SiO 2电介质膜的方法中，供给到等离子体CVD装置的进料气体不仅包括SiH 4气体，O 2气体，CF 4气体和Ar气体，而且包括CO 2气体， 能够独立地控制进料气体中所含的碳和氟的量，以形成浓度范围为4.0×10 21原子/ cc〜1.0×10 22原子/ cc的氟等离子体CVD硅系Si​​O 2介质膜 ，浓度范围为3.0×1019原子/ cc至1.0×1021原子/ cc的碳。 因此，获得具有低介电常数和足够的“耐湿性”的等离子体CVD硅基SiO 2电介质膜。

公开(公告)号：US08592303B2

公开(公告)日：2013-11-26

申请号：US12715088

申请日：2010-03-01

申请人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

发明人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

IPC分类号： H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.

摘要翻译： 提供一种布线结构及其制造方法，其中在形成半导体元件的基板上形成金属布线的多层布线的布线结构中，从而获得元件的连接，不会损坏绝缘性能 在多孔绝缘膜中形成细小的金属布线的情况下，可以通过发生漏电流而在邻接布线之间形成邻接布线之间的绝缘电阻特性。 在形成半导体元件的基板上的金属布线结构中，在层间绝缘膜和金属布线之间形成绝缘阻挡层413。 绝缘阻挡层能够减少邻接布线之间的泄漏电流并提高绝缘可靠性。

公开(公告)号：US07701060B2

公开(公告)日：2010-04-20

申请号：US10558367

申请日：2004-05-28

申请人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

发明人： Munehiro Tada ,  Yoshihiro Hayashi ,  Yoshimichi Harada ,  Fuminori Ito ,  Hiroto Ohtake ,  Tatsuya Usami

IPC分类号： H01L23/48

CPC分类号： H01L23/53295 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer 413 is formed between an interlayer insulation film and the metal wiring, in the metal wiring structure on the substrate forming the semiconductor element. The insulation barrier layer enables to reduce leakage current between the abutting wirings and to elevate the insulation credibility.

摘要翻译： 提供一种布线结构及其制造方法，其中在形成半导体元件的基板上形成金属布线的多层布线的布线结构中，从而获得元件的连接，不会损坏绝缘性能 在多孔绝缘膜中形成细小的金属布线的情况下，可以通过发生漏电流而在邻接布线之间形成邻接布线之间的绝缘电阻特性。 在形成半导体元件的基板上的金属布线结构中，在层间绝缘膜和金属布线之间形成绝缘阻挡层413。 绝缘阻挡层能够减少邻接布线之间的泄漏电流并提高绝缘可靠性。

公开(公告)号：US20070052101A1

公开(公告)日：2007-03-08

申请号：US11359440

申请日：2006-02-23

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film.

摘要翻译： 半导体器件包括互连结构，其包括由含铜金属制成的第一互连，覆盖第一互连的上部的第一Cu硅化物层，设置在Cu硅化物层的上部上的导电第一插塞和 连接到所述第一互连件，覆盖所述第一插塞的上部的Cu硅化物层，设置在所述侧壁上的所述第一多孔MSQ膜，所述第一多孔MSQ膜从所述第一互连通过所述第一插塞形成以覆盖所述第一互连的侧壁， 第一互连的上部和第一插塞的侧壁，以及设置在第一多孔MSQ膜下方的第一SiCN膜，以与第一互连的侧壁的下部相接触，并且具有比 第一多孔MSQ膜。

公开(公告)号：US07057286B2

公开(公告)日：2006-06-06

申请号：US10260947

申请日：2002-09-30

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23/28

CPC分类号： H01L21/76835 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76832 ,  H01L2221/1036

摘要： A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

公开(公告)号：US07045898B2

公开(公告)日：2006-05-16

申请号：US10438887

申请日：2003-05-16

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76849

摘要： There is presented a structure in which outlines of a metal interconnection 111 that is laid in an interlayer insulating film are covered with a barrier metal film 110. As the material for the barrier metal film 110, TaN or the like is utilized.

公开(公告)号：US20050179137A1

公开(公告)日：2005-08-18

申请号：US11101416

申请日：2005-04-08

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23/532 ,  H01L23/52

CPC分类号： H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon carbon nitride film is formed on an interlayer dielectric film having Si—H bonds and a Cu interconnection. The silicon carbon nitride film has the role of blocking moisture absorption and prevents deterioration associated with the moisture absorption by a lower-layer insulating film and a Cu film, thereby suppressing an increase in the capacitance between interconnections or via resistance. The effect is great especially when the nitrogen concentration of the silicon carbon nitride film is not less than 10 atm % but less than 35 atm %. Between the interlayer dielectric film having Si—H bonds and the Cu interconnection is interposed a laminated film of a Ta film and a TaN film as a barrier metal film in such a manner that the TaN film becomes on the side of the interlayer dielectric film.

摘要翻译： 在具有Si-H键和Cu互连的层间电介质膜上形成碳氮化硅膜。 硅氮化硅膜具有阻止吸湿的作用，并且防止与下层绝缘膜和Cu膜的吸湿相关的劣化，从而抑制互连或通孔电阻之间的电容的增加。 特别是当氮化硅氮化物膜的氮浓度不小于10atm％但小于35atm％时，效果非常好。 在具有Si-H键的层间电介质膜和Cu互连之间插入有Ta膜和TaN膜的叠层膜作为阻挡金属膜，使得TaN膜成为层间电介质膜的一侧。

公开(公告)号：US06930036B2

公开(公告)日：2005-08-16

申请号：US10695159

申请日：2003-10-28

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76832 ,  H01L2221/1036

摘要： A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.

摘要翻译： 在半导体器件中制造多电平互连结构的方法包括在第一层Cu层上连续形成抗扩散膜和层间电介质膜的步骤，在层间绝缘膜上形成第一至第三硬掩模膜， 通过使用第一硬掩模来形成第一硬掩模以蚀刻层间电介质膜，通过使用第三硬掩模膜来蚀刻第一和第二硬掩模膜和层间绝缘膜的顶部以形成沟槽， 扩散膜形成通孔。 第一硬掩模膜在去除第二和第三硬掩模膜期间保护层间电介质膜。

公开(公告)号：US06670709B2

公开(公告)日：2003-12-30

申请号：US09779584

申请日：2001-02-09

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23485

CPC分类号： H01L21/76829 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first HSQ film composed of a Si—O-based film with a low dielectric constant is formed on a first wiring via a protective insulation film, and the surface of this first HSQ film is reformed to form a first SRO layer. Then, a second HSQ film is formed on this first SRO layer, and the surface of the second HSQ film is reformed to form a second SRO layer. Next, a via-hole is formed within a predetermined region, which reaches the protective insulation film on the first wiring. Then, wiring trenches forming a second wiring are formed within predetermined regions of the second HSQ film and the second SRO film while using the first SRO film as an etching stopper film. Thereafter, the protective insulation film at the bottom of the via-hole is etched and removed, and the wiring trenches and the via-hole are embedded with a conductive film. Then, the conductive film on the second SRO layer is removed while using the second SRO layer as a CMP stopper film.

摘要翻译： 通过保护绝缘膜在第一布线上形成由具有低介电常数的Si-O基膜构成的第一HSQ膜，并将该第一HSQ膜的表面重整形成第一SRO层。 然后，在该第一SRO层上形成第二HSQ膜，将第二HSQ膜的表面重新形成第二SRO层。 接下来，在到达第一布线上的保护绝缘膜的预定区域内形成通孔。 然后，在使用第一SRO膜作为蚀刻停止膜的同时，在第二HSQ膜和第二SRO膜的预定区域内形成形成第二布线的布线沟槽。 此后，蚀刻去除通孔底部的保护绝缘膜，并且布线沟槽和通孔嵌入导电膜。 然后，在使用第二SRO层作为CMP阻挡膜的同时去除第二SRO层上的导电膜。

公开(公告)号：US06514852B2

公开(公告)日：2003-02-04

申请号：US09910994

申请日：2001-07-23

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76832 ,  H01L2221/1036

摘要： A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.