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    MEMORY DEVICE WITH ON-DIE CACHE
    63.
    发明公开
    MEMORY DEVICE WITH ON-DIE CACHE 审中-公开

    公开(公告)号：US20240202119A1

    公开(公告)日：2024-06-20

    申请号：US18590173

    申请日：2024-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Shivam Swami

    IPC: G06F12/0802 ,  G06F3/06

    CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2212/22 ,  G06F2212/221

    Abstract: An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.

    METHODS FOR PERFORMING PROCESSING-IN-MEMORY OPERATIONS, AND RELATED SYSTEMS
    64.
    发明公开
    METHODS FOR PERFORMING PROCESSING-IN-MEMORY OPERATIONS, AND RELATED SYSTEMS 审中-公开

    公开(公告)号：US20240192953A1

    公开(公告)日：2024-06-13

    申请号：US18582520

    申请日：2024-02-20

    Applicant: Micron Technology, Inc.

    Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

    IPC: G06F9/30 ,  G06F7/544

    CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30032 ,  G06F9/30043

    Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

    SEQUENCE ALIGNMENT WITH MEMORY ARRAYS
    65.
    发明公开
    SEQUENCE ALIGNMENT WITH MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240086100A1

    公开(公告)日：2024-03-14

    申请号：US17931262

    申请日：2022-09-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

    Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

    IN-MEMORY ASSOCIATIVE PROCESSING SYSTEM
    68.
    发明申请
    IN-MEMORY ASSOCIATIVE PROCESSING SYSTEM 有权

    公开(公告)号：US20230069790A1

    公开(公告)日：2023-03-02

    申请号：US17577977

    申请日：2022-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Justin Eno ,  Brian Hirano

    IPC: G06F9/30 ,  G06F13/16

    Abstract: Methods, systems, and devices for in-memory associative processing are described. An apparatus may receive a set of instructions that indicate a first vector and a second vector as operands for a computational operation. The apparatus may select, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing. The apparatus may write the first vector and the second vector to a set of planes each comprising an array of content-addressable memory cells based on the selected vector mapping scheme.

    Distributed Computing based on Memory as a Service
    69.
    发明申请
    Distributed Computing based on Memory as a Service 有权

    公开(公告)号：US20230004502A1

    公开(公告)日：2023-01-05

    申请号：US17943739

    申请日：2022-09-13

    Applicant: Micron Technology, Inc.

    Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

    IPC: G06F12/10 ,  H04L67/1097 ,  H04W84/04

    Abstract: Systems, methods and apparatuses of distributed computing based on memory as a service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

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