公开(公告)号：US11797186B2

公开(公告)日：2023-10-24

申请号：US16951299

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for latency offset for frame-based communications are described. A memory system may include a host device and a memory device that communicate using frames based on a frame period of a frame clock. The memory device may receive a read command and a write command from the host device, and determine a read latency and a write latency corresponding to the received commands. The memory device may also determine an additional offset latency to add to the write latency to avoid bus contention between read data and write data associated with the read command and the write command, respectively. The offset latency may correspond to an integer quantity of clock periods, which may be less than the frame period.

公开(公告)号：US20230206969A1

公开(公告)日：2023-06-29

申请号：US18086991

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Brent Keeth ,  Matthew A. Prather

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/109 ,  G11C7/1084 ,  G11C7/222

Abstract: Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.

公开(公告)号：US11658156B2

公开(公告)日：2023-05-23

申请号：US17225675

申请日：2021-04-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  G11C5/10 ,  G11C29/12 ,  H01L25/18

CPC classification number: H01L25/0657 ,  G11C5/10 ,  G11C29/12 ,  H01L23/481 ,  H01L24/16 ,  H01L24/24 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/24225 ,  H01L2225/0652 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/1441

Abstract: Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device.

公开(公告)号：US11644982B2

公开(公告)日：2023-05-09

申请号：US17453787

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Naveh Malihi

IPC: G06F12/00 ,  G06F3/06 ,  G06F21/62

CPC classification number: G06F3/0622 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F21/6245

Abstract: Apparatuses and methods related to tracking unauthorized access commands for memory. Identifying unauthorized memory access can include verifying whether an access command is authorized to access a protected region of a memory array. The authorization can be verified utilizing a key and a memory address corresponding to the access command. If an access command is authorized to access a protected region, then a row of the memory array corresponding to the access command can be activated. If an access command is not authorized to access the protected region, then an access count can be incremented to signify the unauthorized access command.

公开(公告)号：US20230127970A1

公开(公告)日：2023-04-27

申请号：US18087328

申请日：2022-12-22

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Matthew A. Prather ,  Brent Keeth ,  Frank F. Ross ,  Daniel Benjamin Stewart ,  Randall J. Rooney

IPC: G11C7/10 ,  G11C7/22

Abstract: The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.

公开(公告)号：US20220404985A1

公开(公告)日：2022-12-22

申请号：US17863994

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth

IPC: G06F3/06

Abstract: Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.

公开(公告)号：US20220382631A1

公开(公告)日：2022-12-01

申请号：US17883027

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  Brent Keeth

IPC: G06F11/10 ,  G06F11/07

Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.

公开(公告)号：US20220342814A1

公开(公告)日：2022-10-27

申请号：US17861627

申请日：2022-07-11

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US11409601B1

公开(公告)日：2022-08-09

申请号：US17158874

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  Brent Keeth

IPC: G06F11/07 ,  G06F11/10

Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.

公开(公告)号：US11386004B2

公开(公告)日：2022-07-12

申请号：US16797618

申请日：2020-02-21

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G11C16/04 ,  G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  G06F12/02

Abstract: Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.