公开(公告)号：US11960744B2

公开(公告)日：2024-04-16

申请号：US17163683

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0679

Abstract: A semiconductor device includes a memory partition. The semiconductor device further includes a plurality of registers. A first register of the plurality of registers, when in operation, controls an operation associated with the memory partition. The semiconductor device additionally includes a memory controller. When in operation, the memory controller accesses a first location of the memory partition concurrently with accessing the first register.

公开(公告)号：US11900999B2

公开(公告)日：2024-02-13

申请号：US17702562

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C11/00 ,  G11C13/00 ,  G06F9/30

CPC classification number: G11C13/003 ,  G06F9/30116 ,  G11C13/004 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/0069

Abstract: A memory system may include multiple memory cells to store logical data and cycle tracking circuitry to track a number of cycles associated the memory cells. The cycles may be representative of one or more past accesses of the memory cells. The memory system may also include control circuitry to access the memory cells. Accessing of the memory cell may include a read operation, a write operation, or both. During the accessing of the memory cell, the control circuitry may determine a voltage parameter of the access based at least in part on the tracked number of cycles.

公开(公告)号：US20230395569A1

公开(公告)日：2023-12-07

申请号：US18202249

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Hari Giduturi ,  Yeon-Chang Hahm

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L2924/1431 ,  H01L23/528 ,  H01L24/08 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2224/08112 ,  H01L2224/0903 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H10B80/00

Abstract: Semiconductor devices, such as memory devices, and associated systems and methods, are disclosed herein. A representative memory device includes a substrate including circuitry, back-end contacts electrically coupled to the circuitry, and front-end contacts. The front-end contacts are configured to receive electrical signals from an external device via a front-end interface. Individual ones of the front-end contacts are electrically coupled to and aligned along an axis with corresponding ones of the back-end contacts.

公开(公告)号：US11749342B2

公开(公告)日：2023-09-05

申请号：US17549390

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： John Fredric Schreck ,  Hari Giduturi

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/0028

Abstract: An architecture of the memory device may leverage a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loads in accessing a memory cell. A memory cell of such a memory device may experience a total resistance including a transmission path resistance associated with the respective access lines of the memory cell and an added compensatory resistance. The foregoing memory device may leverage a spike mitigation scheme to mitigate the harmful effect of a voltage and/or rush current to the near memory cells of the memory device. In addition, spike mitigation circuitry may include coupling a resistor on access lines near the respective decoders. Further, spike mitigation circuitry may include coupling a resistor between the decoders.

公开(公告)号：US11605418B2

公开(公告)日：2023-03-14

申请号：US17080310

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Michael McCrate ,  Robert John Gleixner ,  Hari Giduturi ,  Ramin Ghodsi

IPC: G11C13/00 ,  G11C11/408 ,  G11C11/4091

Abstract: The application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. The application is also directed to writing and reading memory cell pairs.

公开(公告)号：US20220399055A1

公开(公告)日：2022-12-15

申请号：US17864004

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

IPC: G11C13/00

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

公开(公告)号：US11527286B2

公开(公告)日：2022-12-13

申请号：US17375441

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Mingdong Cui ,  Nathan Joseph Sirocka ,  Hari Giduturi

IPC: G11C7/12 ,  G11C8/08 ,  G11C13/00

Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.

公开(公告)号：US20220359005A1

公开(公告)日：2022-11-10

申请号：US17869649

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C29/50 ,  G11C11/4074 ,  G11C11/409

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US11348637B2

公开(公告)日：2022-05-31

申请号：US17008254

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C16/10 ,  G11C13/00 ,  G06F3/06

Abstract: Memory device systems and methods for using methods include multiple access lines arranged in a grid. Multiple memory cells are located at intersections of the access lines in the grid. Multiple drivers are included with each configured to transmit a corresponding signal to respective memory cells of the multiple memory cells. Remapping circuitry is configured to remap a near memory cell of the multiple memory cells to a far memory cell of the multiple memory cells. The near memory cell is relatively nearer to a respective driver of the multiple drivers than the far memory cell is to a respective driver of the multiple drivers.

公开(公告)号：US11309024B2

公开(公告)日：2022-04-19

申请号：US17005739

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Hari Giduturi

IPC: G11C11/00 ,  G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude that can be greater than the first magnitude.