公开(公告)号：US11315877B2

公开(公告)日：2022-04-26

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20220028996A1

公开(公告)日：2022-01-27

申请号：US17496715

申请日：2021-10-07

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett A. McTeer ,  John Mark Meldrim

IPC: H01L29/49 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US11121143B2

公开(公告)日：2021-09-14

申请号：US16422150

申请日：2019-05-24

Applicant: Micron Technology, inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout ,  Rita J. Klein

IPC: H01L27/11529 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11556

Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210057440A1

公开(公告)日：2021-02-25

申请号：US16550250

申请日：2019-08-25

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Daniel Billingsley ,  Indra V. Chary ,  Rita J. Klein

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.

公开(公告)号：US20210050361A1

公开(公告)日：2021-02-18

申请号：US16539700

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Rita J. Klein ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Electronic devices (e.g., semiconductor devices, which may be configured for 3D NAND memory devices), comprise pillars extending through a stack of alternating conductive tiers and insulative tiers. The conductive tiers, which may include control gates for access lines (e.g., word lines), include conductive rails along an outer sidewall of the conductive tiers, distal from the pillars extending through the conductive tiers. The conductive rails protrude laterally beyond outer sidewalls of the insulative tiers. The conductive rails increase the amount of conductive material than may otherwise be in the conductive tiers, which may enable the conductive material to exhibit a lower electrical resistance, improving operational performance of the electronic devices.

公开(公告)号：US20210005732A1

公开(公告)日：2021-01-07

申请号：US16458400

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20200168624A1

公开(公告)日：2020-05-28

申请号：US16203200

申请日：2018-11-28

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Rita J. Klein

IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

公开(公告)号：US20180204851A1

公开(公告)日：2018-07-19

申请号：US15924143

申请日：2018-03-16

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L27/11582 ,  H01L29/49 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

公开(公告)号：US20150333143A1

公开(公告)日：2015-11-19

申请号：US14281569

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。