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    METHODS OF FORMING SEMICONDUCTOR DEVICES USING ASPECT RATIO DEPENDENT ETCHING EFFECTS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    61.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES USING ASPECT RATIO DEPENDENT ETCHING EFFECTS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20200185389A1

    公开(公告)日：2020-06-11

    申请号：US16793888

    申请日：2020-02-18

    Applicant: Micron Technology, Inc.

    Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

    IPC: H01L27/108 ,  H01L21/308

    Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

    MEMORY ARRAYS
    62.
    发明申请
    MEMORY ARRAYS 审中-公开

    公开(公告)号：US20200176465A1

    公开(公告)日：2020-06-04

    申请号：US16204224

    申请日：2018-11-29

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Richard J. Hill ,  Yi Fang Lee ,  Martin C. Roberts

    IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/11514 ,  H01L27/11585

    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.

    Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related semiconductor devices
    64.
    发明授权
    Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related semiconductor devices 有权

    公开(公告)号：US10593678B1

    公开(公告)日：2020-03-17

    申请号：US16111499

    申请日：2018-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

    IPC: H01L27/108 ,  H01L21/308 ,  G11C11/408

    Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

    Semiconductor devices
    65.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10566332B2

    公开(公告)日：2020-02-18

    申请号：US16192097

    申请日：2018-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Kuo-Chen Wang ,  Shih-Fan Kuan ,  Lars Heineck ,  Sanh D. Tang

    IPC: H01L27/108 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

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