公开(公告)号：US20200159674A1

公开(公告)日：2020-05-21

申请号：US16192068

申请日：2018-11-15

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Sean S. Eilert ,  Bryce D. Cook

IPC: G06F12/14 ,  G06F12/02

Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

公开(公告)号：US20240420757A1

公开(公告)日：2024-12-19

申请号：US18820840

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

公开(公告)号：US20240233870A9

公开(公告)日：2024-07-11

申请号：US18049506

申请日：2022-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G16B30/10 ,  G16B50/00

CPC classification number: G16B30/10 ,  G16B50/00

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

公开(公告)号：US12026051B2

公开(公告)日：2024-07-02

申请号：US17861013

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Justin Eno ,  William A. Melton ,  Sean S. Eilert

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/30

CPC classification number: G06F11/1068 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1064 ,  G06F11/3037

Abstract: Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.

公开(公告)号：US20240192892A1

公开(公告)日：2024-06-13

申请号：US18531267

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Patrick Estep ,  Sean S. Eilert ,  Ameen D. Akel

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0689

Abstract: Systems, apparatuses, and methods related to data reconstruction based on queue depth comparison are described. To avoid accessing the “congested” channel, a read command to access the “congested” channel can be executed by accessing the other relatively “idle” channels and utilize data read from the “idle” channels to reconstruct data corresponding to the read command.

公开(公告)号：US12001708B2

公开(公告)日：2024-06-04

申请号：US17647944

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Justin Eno ,  Brian Hirano

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for in-memory associative processing for vectors are described. A device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. The first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. The device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. The second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.

公开(公告)号：US11947453B2

公开(公告)日：2024-04-02

申请号：US17100453

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Ameen D. Akel ,  Shivam Swami

IPC: G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2212/22 ,  G06F2212/221

Abstract: An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.

公开(公告)号：US11934824B2

公开(公告)日：2024-03-19

申请号：US16841222

申请日：2020-04-06

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Sivagnanam Parthasarathy ,  Shivasankar Gunasekaran ,  Ameen D. Akel

IPC: G06F9/30 ,  G06F7/544

CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30032 ,  G06F9/30043

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

公开(公告)号：US11789797B2

公开(公告)日：2023-10-17

申请号：US17886253

申请日：2022-08-11

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G11C15/04 ,  G06F11/07 ,  G06F11/10 ,  G11C5/06 ,  G11C11/409

CPC classification number: G06F11/076 ,  G06F11/102 ,  G11C5/063 ,  G11C11/409 ,  G11C15/04

Abstract: Methods, systems, and devices for error control for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.

公开(公告)号：US20230267043A1

公开(公告)日：2023-08-24

申请号：US17652231

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: G06F11/10

CPC classification number: G06F11/108

Abstract: Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.