公开(公告)号：US07132703B2

公开(公告)日：2006-11-07

申请号：US11014893

申请日：2004-12-20

申请人： Masahiro Hikita ,  Manabu Yanagihara

发明人： Masahiro Hikita ,  Manabu Yanagihara

IPC分类号： H01I29/80

CPC分类号： H01L29/66462 ,  H01L29/7783

摘要： A field-effect transistor includes: a carrier supply layer supplying carriers; a Schottky contact layer forming a Schottky barrier; and an intermediate layer formed between the carrier supply layer and the Schottky contact layer. Here, the intermediate layer has an electron affinity which is higher than an electron affinity of the carrier supply layer but lower than an electron affinity of the Schottky contact layer.

摘要翻译： 场效应晶体管包括：提供载体的载流子供应层; 形成肖特基势垒的肖特基接触层; 以及形成在载体供给层和肖特基接触层之间的中间层。 这里，中间层的电子亲和力高于载流子供给层的电子亲和力，但低于肖特基接触层的电子亲和力。

公开(公告)号：US06797996B1

公开(公告)日：2004-09-28

申请号：US10445035

申请日：2003-05-27

申请人： Masahiro Hikita ,  Manabu Yanagihara ,  Tuyoshi Tanaka

发明人： Masahiro Hikita ,  Manabu Yanagihara ,  Tuyoshi Tanaka

IPC分类号： H01L29737

CPC分类号： H01L29/66318 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/365 ,  H01L29/7371

摘要： A compound semiconductor device includes an emitter layer, a base layer which is in contact with the emitter layer and formed of a first compound semiconductor, a collector layer which is in contact with the base layer and formed of a second compound semiconductor having a wider bandgap than that of the first compound semiconductor. In the device, a delta doped layer having a higher concentration of an impurity than that of the collector layer is formed at the heterojunction interface between the collector layer and the base layer or in a region of the collector layer located at about 10 nm or less from the heterojunction interface with the base layer.

摘要翻译： 化合物半导体器件包括发射极层，与发射极层接触并由第一化合物半导体形成的基极层，与基极层接触并由具有较宽带隙的第二化合物半导体形成的集电极层 比第一化合物半导体。 在器件中，在集电极层和基极层之间的异质结界面处或在位于约10nm以下的集电极层的区域中形成杂质浓度高于集电极层的Δ掺杂层 从与基层的异质结界面。

公开(公告)号：US5523623A

公开(公告)日：1996-06-04

申请号：US399180

申请日：1995-03-06

申请人： Manabu Yanagihara ,  Akiyoshi Tamura

发明人： Manabu Yanagihara ,  Akiyoshi Tamura

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L29/45 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L21/28575 ,  H01L29/452 ,  H01L29/7371

摘要： An ohmic electrode for a p-type III-V compound semiconductor is disclosed. The ohmic electrode formed on a p-type III-V compound semiconductor layer includes nickel (Ni), titanium (Ti), and platinum (Pt) as main components in an interface between the ohmic electrode and the p-type III-V compound semiconductor layer.

摘要翻译： 公开了一种用于p型III-V族化合物半导体的欧姆电极。 形成在p型III-V族化合物半导体层上的欧姆电极包括镍（Ni），钛（Ti）和铂（Pt）作为欧姆电极和p型III-V族化合物之间界面的主要成分 半导体层。

公开(公告)号：US5166081A

公开(公告)日：1992-11-24

申请号：US549589

申请日：1990-06-27

申请人： Masanori Inada ,  Kazuo Eda ,  Yorito Ota ,  Atsushi Nakagawa ,  Manabu Yanagihara

发明人： Masanori Inada ,  Kazuo Eda ,  Yorito Ota ,  Atsushi Nakagawa ,  Manabu Yanagihara

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/7371 ,  Y10S148/01 ,  Y10S148/072

摘要： A dummy emitter is formed in the portion corresponding to an emitter region, on a multiplayer structural material comprising layers for forming emitter, base and collector, and using it as mask, an external base region is exposed by etching, and a projection of emitter region is formed, while the dummy emitter is inverted into an emitter electrode, thereby forming an emitter electrode metal layer to cover the whole upper surface of the emitter. Using thus formed emitter electrode metal layer, a base electrode metal layer is formed, by self-alignment, adjacently to the emitter. In other method, on a multilayer structural material, impurities are introduced outside the portion corresponding to the base region of a bipolar transistor in order to insulate, at least, the layer to form the emitter, the layer to form the base, or at most, these layers and the layer to form the collector, and an extension type dummy emitter extending from the emitter portion to the insulating region formed by transforming from the semiconductor material to form the emitter and using it as mask, the external base region is exposed to form a projection coupling the emitter region and insulating region, and the dummy emitter is inverted to transform into an emitter electrode metal layer to cover the whole upper surface of the projection.

公开(公告)号：US08526207B2

公开(公告)日：2013-09-03

申请号：US13158934

申请日：2011-06-13

申请人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Manabu Yanagihara ,  Ayanori Ikoshi

发明人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Manabu Yanagihara ,  Ayanori Ikoshi

IPC分类号： H02M7/02 ,  H03K17/94 ,  H03K17/687

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H03K17/6871 ,  H03K2017/6875 ,  H03K2217/0009

摘要： A semiconductor device 101 in a bi-directional switch includes: a first electrode 109A, a second electrode 109B, a first gate electrode 112A, and a second gate electrode 112B. In a transition period: when the potential of the first electrode 109A is higher than the potential of the second electrode 109B, a voltage lower than the first threshold voltage is applied to the first gate electrode 112A and a voltage higher than the second threshold value voltage is applied to the second gate electrode 112B; and otherwise, a voltage higher than the first threshold value voltage is applied to the first gate electrode, and a voltage lower than the second threshold value voltage is applied to the second gate electrode.

摘要翻译： 双向开关中的半导体器件101包括：第一电极109A，第二电极109B，第一栅电极112A和第二栅电极112B。 在过渡期间：当第一电极109A的电位高于第二电极109B的电位时，将低于第一阈值电压的电压施加到第一栅电极112A，并且施加高于第二阈值电压 施加到第二栅电极112B; 否则，将高于第一阈值电压的电压施加到第一栅电极，并且将低于第二阈值电压的电压施加到第二栅电极。

公开(公告)号：US08405126B2

公开(公告)日：2013-03-26

申请号：US13196512

申请日：2011-08-02

申请人： Daisuke Shibata ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke Shibata ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L29/778

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

摘要翻译： 半导体器件包括形成在衬底上的半导体层堆叠，形成在半导体层堆叠上的第一欧姆电极和第二欧姆电极，并且彼此间隔开，形成在第一欧姆电极和第二欧姆电极之间的第一控制层 第二欧姆电极和形成在第一控制层上的第一栅电极。 第一控制层包括下层，形成在下层上的中间层，并且具有比下层更低的杂质浓度，以及形成在中间层上的上层，并且具有比中间层更高的杂质浓度 层。

公开(公告)号：US08148752B2

公开(公告)日：2012-04-03

申请号：US13021118

申请日：2011-02-04

申请人： Ayanori Ikoshi ,  Shingo Hashizume ,  Masahiro Hikita ,  Hiroto Yamagiwa ,  Manabu Yanagihara

发明人： Ayanori Ikoshi ,  Shingo Hashizume ,  Masahiro Hikita ,  Hiroto Yamagiwa ,  Manabu Yanagihara

IPC分类号： H01L29/778

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/41758

摘要： A field effect transistor includes a semiconductor stack formed on a substrate, and having a first nitride semiconductor layer and a second nitride semiconductor layer. A source electrode and a drain electrode are formed on the semiconductor stack so as to be separated from each other. A gate electrode is formed between the source electrode and the drain electrode so as to be separated from the source electrode and the drain electrode. A hole injection portion is formed near the drain electrode. The hole injection portion has a p-type third nitride semiconductor layer, and a hole injection electrode formed on the third nitride semiconductor layer. The hole injection electrode and the drain electrode have substantially the same potential.

摘要翻译： 场效应晶体管包括形成在衬底上的半导体堆叠，并且具有第一氮化物半导体层和第二氮化物半导体层。 源电极和漏电极形成在半导体堆叠上以便彼此分离。 在源电极和漏电极之间形成栅电极，以与源电极和漏电极分离。 在漏电极附近形成空穴注入部。 空穴注入部分具有p型第三氮化物半导体层和形成在第三氮化物半导体层上的空穴注入电极。 空穴注入电极和漏电极具有大致相同的电位。

公开(公告)号：US20110284928A1

公开(公告)日：2011-11-24

申请号：US13196512

申请日：2011-08-02

申请人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Daisuke SHIBATA ,  Tatsuo Morita ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L29/778 ,  H01L27/06

CPC分类号： H01L29/7783 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

摘要翻译： 半导体器件包括形成在衬底上的半导体层堆叠，形成在半导体层堆叠上的第一欧姆电极和第二欧姆电极，并且彼此间隔开，形成在第一欧姆电极和第二欧姆电极之间的第一控制层 第二欧姆电极和形成在第一控制层上的第一栅电极。 第一控制层包括下层，形成在下层上的中间层，并且具有比下层更低的杂质浓度，以及形成在中间层上的上层，并且具有比中间层更高的杂质浓度 层。

公开(公告)号：US20110193171A1

公开(公告)日：2011-08-11

申请号：US12905801

申请日：2010-10-15

申请人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Ayanori Ikoshi ,  Manabu Yanagihara ,  Yasuhiro Uemoto

发明人： Hiroto Yamagiwa ,  Shingo Hashizume ,  Ayanori Ikoshi ,  Manabu Yanagihara ,  Yasuhiro Uemoto

IPC分类号： H01L27/088

CPC分类号： H01L29/7786 ,  H01L27/0266 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/8124 ,  H01L29/861

摘要： A semiconductor device includes a first transistor formed on a first element region, and a first protecting element including a second transistor formed on a second element region. A second protecting element ohmic electrode is connected to a first gate electrode, a first protecting element ohmic electrode is connected to a first ohmic electrode, and a first protecting element gate electrode is connected to at least one of the first protecting element ohmic electrode and the second protecting element ohmic electrode. The second element region is smaller in area than the first element region.

摘要翻译： 半导体器件包括形成在第一元件区上的第一晶体管和包括形成在第二元件区上的第二晶体管的第一保护元件。 第二保护元件欧姆电极连接到第一栅电极，第一保护元件欧姆电极连接到第一欧姆电极，第一保护元件栅电极连接至第一保护元件欧姆电极和 第二保护元件欧姆电极。 第二元件区域的面积小于第一元件区域。

公开(公告)号：US20100213503A1

公开(公告)日：2010-08-26

申请号：US12681567

申请日：2009-07-10

申请人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tatsuo Morita ,  Yasuhiro Uemoto

发明人： Manabu Yanagihara ,  Kazushi Nakazawa ,  Tatsuo Morita ,  Yasuhiro Uemoto

IPC分类号： H01L29/747

CPC分类号： H01L27/088 ,  H01L23/481 ,  H01L23/4824 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7786 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

摘要翻译： 双向开关包括多个单元电池11，其包括第一欧姆电极15，第一栅极电极17，第二栅极电极18和第二欧姆电极16.第一栅电极15经由第一互连线31电连接到 第一栅极电极焊盘43.第二栅电极18经由第二互连32电连接到第二栅极电极焊盘44.单元电池11包括与第一栅电极焊盘43的布线距离最短的第一栅电极17 包括与第二栅电极焊盘44的互连距离最短的第二栅电极18。