公开(公告)号：US07307346B2

公开(公告)日：2007-12-11

申请号：US10847901

申请日：2004-05-18

申请人： Erdem Kaltalioglu ,  Christian Pils

发明人： Erdem Kaltalioglu ,  Christian Pils

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3171 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/312 ,  H01L21/3144 ,  H01L21/76801 ,  H01L21/76829 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： A semiconductor device includes a substrate with an active area. A last level interconnect capping layer is disposed over the active area. A buffer layer/crack stop layer overlies the last level interconnect capping layer and a passivation layer overlies the buffer layer/crack stop layer. Also, a contact pad (e.g., probe pad, wire bond pad or flip-chip pad) overlies the passivation layer.

摘要翻译： 半导体器件包括具有有源区的衬底。 最后一级互连覆盖层设置在有效区域上。 缓冲层/裂纹停止层覆盖在最后一级互连覆盖层上，钝化层覆盖在缓冲层/裂纹停止层上。 此外，接触焊盘（例如，探针焊盘，引线接合焊盘或倒装芯片焊盘）覆盖钝化层。

公开(公告)号：US20060231955A1

公开(公告)日：2006-10-19

申请号：US11105879

申请日：2005-04-14

申请人： Klaus Herold ,  Erdem Kaltalioglu

发明人： Klaus Herold ,  Erdem Kaltalioglu

IPC分类号： H01L23/52

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having conductive lines with extended ends and methods of extending conductive line ends by a variable distance are disclosed. An end of a first conductive feature of an interconnect structure is extended by a first distance, and an end of a second conductive feature of the interconnect structure is extended by a second distance, the second distance being different than the first distance. Ends of conductive features that are positioned close to adjacent conductive features are preferably not extended.

摘要翻译： 公开了具有延伸端的导电线的半导体器件和将导线端部延伸可变距离的方法。 互连结构的第一导电特征的端部延伸第一距离，并且互连结构的第二导电特征的端部延伸第二距离，第二距离不同于第一距离。 位于靠近相邻导电特征的导电特征端部优选地不延伸。

公开(公告)号：US06613664B2

公开(公告)日：2003-09-02

申请号：US09751552

申请日：2000-12-28

申请人： Hans-Joachin Barth ,  Erdem Kaltalioglu

发明人： Hans-Joachin Barth ,  Erdem Kaltalioglu

IPC分类号： H01L214763

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76852 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-layer integrated circuit (400) and method of manufacturing thereof having barbed vias (427) connecting conductive lines (468, 408). Circuit (400) includes a first dielectric layer (404) deposited on a substrate (402) and conductive lines (408) formed in the first dielectric layer (404). A second dielectric layer (462) is deposited over the first dielectric layer (404). Barbed vias (427) are formed having a substantially cylindrical portion (424) within the second dielectric layer (462) and a barbed portion (426) within conductive lines (408). Conductive lines (468) are formed over the barbed vias (427) within a the second dielectric layer (462). A region of the barbed via (427) barbed portion (406) extends beneath the second dielectric layer (462).

公开(公告)号：US08890560B2

公开(公告)日：2014-11-18

申请号：US13291185

申请日：2011-11-08

申请人： Erdem Kaltalioglu

发明人： Erdem Kaltalioglu

IPC分类号： G01R31/26 ,  G01R31/28 ,  H01L23/58 ,  H01L21/66

CPC分类号： G01R31/2896 ,  G01R31/2601 ,  G01R31/2858 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.

摘要翻译： 公开了用于半导体器件的裂纹传感器，半导体器件，半导体器件的制造方法以及半导体器件的测试方法。 在一个实施例中，裂纹传感器包括靠近集成电路的周边设置的导电结构。 导电结构形成在集成电路的至少一个导电材料层中。 导电结构包括第一端和第二端。 第一端子耦合到导电结构的第一端，并且第二端子耦合到导电结构的第二端。

公开(公告)号：US08610238B2

公开(公告)日：2013-12-17

申请号：US12963254

申请日：2010-12-08

申请人： Erdem Kaltalioglu ,  Hermann Wendt

发明人： Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L21/70 ,  H01L21/00

CPC分类号： H01L21/78 ,  H01L21/31116

摘要： Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

摘要翻译： 公开了形成裂纹停止沟槽的结构和方法。 该方法包括形成设置在衬底的单元区域中的有源区，由切割通道分离的单元区域，以及在衬底上形成后端（BEOL）层，在单元区域和切割通道上形成BEOL层。 然后通过蚀刻围绕单元区域的一部分BEOL层，形成围绕单元区域的裂纹停止沟槽。 晶片沿着切割通道切割。

公开(公告)号：US08309435B2

公开(公告)日：2012-11-13

申请号：US13160214

申请日：2011-06-14

申请人： Erdem Kaltalioglu ,  Michael Beck

发明人： Erdem Kaltalioglu ,  Michael Beck

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

摘要翻译： 公开了用于半导体器件，半导体器件和制造半导体器件的方法的裂纹停止。 在一个实施例中，用于半导体器件的阻挡结构包括多个基本上V形的区域。 多个基本V形区域中的每一个被设置成与多个基本V形区域中的另一个相邻。

公开(公告)号：US08138539B2

公开(公告)日：2012-03-20

申请号：US11947591

申请日：2007-11-29

申请人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

IPC分类号： H01L27/108 ,  H01L21/20

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

公开(公告)号：US08062971B2

公开(公告)日：2011-11-22

申请号：US12051644

申请日：2008-03-19

申请人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

发明人： Philipp Riess ,  Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

摘要翻译： 公开了在半导体部件上形成金属化层的结构和方法。 该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。 通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

公开(公告)号：US08008750B2

公开(公告)日：2011-08-30

申请号：US12024758

申请日：2008-02-01

申请人： Erdem Kaltalioglu ,  Michael Beck

发明人： Erdem Kaltalioglu ,  Michael Beck

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device includes a plurality of substantially V-shaped regions. Each of the plurality of substantially V-shaped regions is disposed adjacent another of the plurality of substantially V-shaped regions.

摘要翻译： 公开了用于半导体器件，半导体器件和制造半导体器件的方法的裂纹停止。 在一个实施例中，用于半导体器件的阻挡结构包括多个基本上V形的区域。 多个基本V形区域中的每一个被设置成与多个基本V形区域中的另一个相邻。

公开(公告)号：US20110074033A1

公开(公告)日：2011-03-31

申请号：US12963254

申请日：2010-12-08

申请人： Erdem Kaltalioglu ,  Hermann Wendt

发明人： Erdem Kaltalioglu ,  Hermann Wendt

IPC分类号： H01L23/532

CPC分类号： H01L21/78 ,  H01L21/31116

摘要： Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

摘要翻译： 公开了形成裂纹停止沟槽的结构和方法。 该方法包括形成设置在衬底的单元区域中的有源区，由切割通道分离的单元区域，以及在衬底上形成后端（BEOL）层，在单元区域和切割通道上形成BEOL层。 然后通过蚀刻围绕单元区域的一部分BEOL层，形成围绕单元区域的裂纹停止沟槽。 晶片沿着切割通道切割。