摘要:
For reducing the scale of a multiplexer, a lower speed ATM interface block, an interface block for SDT mode circuit emulation, and an interface block for UDT mode circuit emulation perform processing for terminating services provided by lower speed transmission lines accommodated therein, and part of AAL processing, which is pre-processing depending on a service, for generating ATM cells from signals received by a terminated service, and send the processed signal to a higher speed line interface using a previously assigned time slot on a time-division bus. The higher speed line interface once stores the signals received from the time-division bus in a buffer, and subsequently performs certain processing including a common portion for respective signals for generating therefrom ATM cells in which the signals are stored in payloads. The generated ATM cells are multiplexed and transmitted onto a higher speed transmission line.
摘要:
An optical transmission system accomplishes optical transmission over a long distance by combining a multiplexing line terminal with optical amplifiers, linear repeaters, and regenerators with optical amplifiers combined together. The system also accomplishes the optical transmission over a short distance by directly connecting the linear terminals therebetween, with an electric-to-optic converter replaced by an electric-to-optic converter having a semiconductor amplifier, with an optic-toelectric converter by an optic-to-electric converter having an avalanche photodiode as light receiver, and with no use of any optical booster amplifier and optical preamplifier in the multiplexing line terminal. With these, the optical transmission system can be easily constructed depending on the transmission distance required.
摘要:
An LAN interface unit and an ATM switch unit cooperate to perform traffic control. A QoS unit monitors circumstances of an input buffer from a multiplexer of the ATM switch by means of a system controller and when an overflow of the input buffer is expected, the LAN interface unit of the multiplexer is instructed to perform traffic control. The LAN interface unit performs traffic control such as limitation of ATM cells inputted in the ATM switch.
摘要:
An optical repeater for realizing transmission of supervisory information of an optical fiber transmission system without the output power of an optical fiber amplifier being reduced, wherein a supervisory optical transmitter and optical receiver with a wavelength which is similar to the wavelength of the pumping light source of the optical fiber amplifier are mounted, and on the input side of the optical repeater, pumping light is multiplexed in the forward direction and a supervisory optical signal, which is multiplexed in wavelength and transmitted, is demultiplexed simultaneously by the first wavelength multi- and demultiplexer and they are received by the supervisory optical receiver, and on the output side of the optical repeater, pumping light is muitiplexed in the reverse direction and a supervisory optical signal outputted from the supervisory optical transmitter is multiplexed by the second wavelength multi- and demultiplexer.
摘要:
First stage and third stage four-input four-output space division switches are arranged before and after a second stage time division switch, and two outputs of the first stage space division switch and two inputs of the third stage space division switch are connected by bypassing the time division switch. The time division switch has n control memories. A first control memory stores connection information in a normal state of each path set in the transmission line, a second control memory stores connection information of a first alternative path when failures occur in a path, and an n-th control memory (n is any integer equal or greater than 3) stores connection information of an (n-1)th alternative path, and a control memory corresponding the a failure pattern is selected from the n control memories for each path.
摘要:
A cell routing method and apparatus in an ATM processing apparatus. The ATM processing apparatus has two or more routing tables associated with address filters of an ATM switch to store routing information for indicating the destination of cell output, and two or more conversion tables associated with VPI conversion circuits for replacing VPI (Virtual Path Identifier) or VCI conversion circuits for replacing VCI (Virtual Channel Identifier) to store information for indicating the VPI or VCI obtained after conversion. In an input interface circuit, selection information indicating which routing table and conversion table out of the above described two or more routing tables and two or more conversion tables should be selected is written into an occupied area within a cell. In a switch circuit, the selection information is read and one routing table is selected out of the above described two or more routing tables on the basis of the selection information thus read, and cell routing is thus performed based on information in the selected routing table. Further, in an output interface circuit, selection information contained in the cell is read and one conversion table is selected out of the above described two or more conversion tables on the basis of the selection information thus read, and VPI conversion or VCI conversion is thus executed based on information in the selected conversion table.
摘要:
A frame aligner and a method and system for control thereof, in which the frame alignment is executed while assuring TSSI (Time Slot Sequence Integrity). In a system for transmitting a plurality of low-speed signals having a frame structure in a high-speed frame, a plurality of candidates for a write start phase for a frame aligner memory are set, and by accessing a common phase memory storing a write start phase shared by low-speed signals requiring phase matching therebetween of all the low-speed signals stored in the high-speed frame, a write start phase is selected from among the candidates for the write start phase for the frame aligner memory.
摘要:
A circuit switching apparatus and method for time division network with various transmission speeds for time-division multiplexing a plurality of circuits including signals at different transmission speeds, transmitting the same onto an input highway, repeatedly recording the transmitted signals in a data memory in a predetermined order, reading respective recorded signals in a predetermined order onto an output highway. An access unit for reading signals from the data memory has an address control memory for storing circuit switching information, a circuit speed control memory for storing transmission speed information for the respective circuits and an address generating section for generating an address for accessing the data memory on the basis of the circuit switching information and the circuit transmission speed information from those memories.
摘要:
Disclosed is a mobile communication system preventing the transmission of acknowledgements at a burst leading to a decrease in throughput caused by detecting the retransmission and the congestion of packets at the protocol of a transport layer. In a mobile communication system including a mobile terminal and gateway equipment for relaying a packet between a communication partner and the mobile terminal, if the gateway equipment receives the acknowledgement from the mobile terminal, the gateway equipment waits the transmission of the received acknowledgement to the communication partner until the estimated transmission time passes from the time at which the gateway equipment receives the previous acknowledgement from the mobile terminal.
摘要:
An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.