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61.发明授权公开(公告)号：US09184382B2
公开(公告)日：2015-11-10
申请号：US12914935
申请日：2010-10-28
CPC分类号： H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1616
摘要： Memristor systems and method for fabricating memristor system are disclosed. In one aspect, a memristor includes a first electrode, a second electrode, and a junction disposed between the first electrode and the second electrode. The junction includes at least one layer such that each layer has a plurality of dopant sub-layers disposed between insulating sub-layers. The sub-layers are oriented substantially parallel to the first and second electrodes.
摘要翻译： 记忆体系统和制造忆阻器系统的方法被公开。 一方面，忆阻器包括第一电极，第二电极和设置在第一电极和第二电极之间的结。 该结包括至少一个层，使得每个层具有设置在绝缘子层之间的多个掺杂剂子层。 子层的取向基本上平行于第一和第二电极。
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公开(公告)号：US08928560B2
公开(公告)日：2015-01-06
申请号：US13424776
申请日：2012-03-20
IPC分类号： G09G3/20
CPC分类号： G09G3/3648 , G09G3/20
摘要： A display matrix may have a resistance switch and a display element formed on a common display substrate. The resistance switch may have a metal insulator transition (MIT) material that has a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance.
摘要翻译： 显示矩阵可以具有形成在公共显示基板上的电阻开关和显示元件。 电阻开关可以具有呈现不连续电阻的具有负差分电阻（NDR）特性的金属绝缘体转变（MIT）材料。
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公开(公告)号：US20140313818A1
公开(公告)日：2014-10-23
申请号：US14345594
申请日：2011-10-28
IPC分类号： H03K19/177 , G11C11/41 , H03K3/037
CPC分类号： G11C11/419 , G11C11/41 , G11C13/0007 , G11C19/28 , G11C2013/0073 , G11C2213/15 , G11C2213/32 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L49/003 , H03K3/037 , H03K3/357 , H03K19/00315 , H03K19/1776
摘要： A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable operating state of the pair is capable of being selected by a programing voltage. Once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device.
摘要翻译： 金属 - 绝缘体相变（MIT）触发器采用一对双稳态工作状态中选择的一个来表示MIT触发器的逻辑状态。 MIT触发器包括具有电流控制的负差分电阻（CC-NDR）的MIT装置，以提供一对双稳态工作状态。 该对的双稳态工作状态能够通过编程电压进行选择。 一旦选择了双稳态操作状态，双稳态操作状态就能够通过施加到MIT设备的偏压来保持。
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公开(公告)号：US08780610B2
公开(公告)日：2014-07-15
申请号：US13560058
申请日：2012-07-27
CPC分类号： G11C13/0069 , G11C13/0007 , G11C14/009 , G11C19/00
摘要： Storing data in a non-volatile latch may include applying a bias voltage to a memristor pair in electrical communication with at least one logic gate and applying a gate voltage to a transmission gate to allow an input voltage to be applied to the at least one logic gate where the input voltage is greater than the bias voltage and the input voltage determines a resistance state of the memristor pair.
摘要翻译： 将数据存储在非易失性锁存器中可以包括将偏置电压施加到与至少一个逻辑门电通信的忆阻器对，并将栅极电压施加到传输门以允许将输入电压施加到至少一个逻辑 输入电压大于偏置电压的栅极，输入电压决定了忆阻器对的电阻状态。
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公开(公告)号：US20140035614A1
公开(公告)日：2014-02-06
申请号：US13563167
申请日：2012-07-31
申请人： Matthew D. Pickett
发明人： Matthew D. Pickett
IPC分类号： H03K17/16
CPC分类号： H03K19/0813 , G06N3/049 , G06N3/0635 , H03K19/0021
摘要： Logic circuits using neuristors is described. In an example, a circuit includes a plurality of neuristors each producing an output voltage spike in response to a super-threshold input voltage. A plurality of impedances couple the plurality of neuristors to form at least one input and an output, the output selectively providing an output voltage spike based on a logical operation of at least one input voltage at the at least one input.
摘要翻译： 描述使用神经元的逻辑电路。 在一个示例中，电路包括多个神经电阻，每个神经电阻响应于超阈值输入电压而产生输出电压尖峰。 多个阻抗耦合所述多个神经元以形成至少一个输入和输出，所述输出基于所述至少一个输入处的至少一个输入电压的逻辑运算选择性地提供输出电压尖峰。
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公开(公告)号：US20140029328A1
公开(公告)日：2014-01-30
申请号：US13560058
申请日：2012-07-27
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C14/009 , G11C19/00
摘要： Storing data in a non-volatile latch may include applying a bias voltage to a memristor pair in electrical communication with at least one logic gate and applying a gate voltage to a transmission gate to allow an input voltage to be applied to the at least one logic gate where the input voltage is greater than the bias voltage and the input voltage determines a resistance state of the memristor pair.
摘要翻译： 将数据存储在非易失性锁存器中可以包括将偏置电压施加到与至少一个逻辑门电通信的忆阻器对，并将栅极电压施加到传输门以允许将输入电压施加到至少一个逻辑 输入电压大于偏置电压的栅极，输入电压决定了忆阻器对的电阻状态。
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公开(公告)号：US20140003139A1
公开(公告)日：2014-01-02
申请号：US13536602
申请日：2012-06-28
IPC分类号： G11C11/00
CPC分类号： G11C11/39 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2213/15 , G11C2213/55 , G11C2213/56
摘要： A memory device includes a first conductive layer, a second conductive layer, an in-bit current limiter including a voltage controlled negative differential resistance (VC-NDR) layer in electrical contact with the first conductive layer and a memristor element in electrical contact with the VC-NDR layer and the second conductive layer. A method for programming a memory device that comprises a VC-NDR device is also provided.
摘要翻译： 存储器件包括第一导电层，第二导电层，包含与第一导电层电接触的电压控制负差动电阻（VC-NDR）层的位内限流器和与该第一导电层电接触的阻尼器元件 VC-NDR层和第二导电层。 还提供了一种用于编程包括VC-NDR设备的存储设备的方法。
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公开(公告)号：US20130106480A1
公开(公告)日：2013-05-02
申请号：US13362538
申请日：2012-01-31
IPC分类号： H03K3/335
CPC分类号： H01L45/146 , G11C13/0007 , G11C2211/5614 , G11C2213/15 , H01L45/04 , H01L45/1233 , H03K3/357
摘要： A metal-insulator transition (MIT) latch includes a first electrode spaced apart from a second electrode and an MIT material disposed between said first and second electrodes. The MIT material comprises a negative differential resistance (NDR) characteristic that exhibits a discontinuous resistance change at a threshold voltage or threshold current. Either the first or second electrode is electrically connected to an electrical bias source regulated to set a resistance phase of the MIT material.
摘要翻译： 金属 - 绝缘体转变（MIT）锁存器包括与第二电极间隔开的第一电极和设置在所述第一和第二电极之间的MIT材料。 MIT材料包括在阈值电压或阈值电流下呈现不连续电阻变化的负差分电阻（NDR）特性。 第一或第二电极电连接到被调节以设定MIT材料的电阻相位的电偏压源。
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公开(公告)号：US08431921B2
公开(公告)日：2013-04-30
申请号：US13130827
申请日：2009-01-13
IPC分类号： H01L29/02
CPC分类号： H01L45/08 , H01L27/2472 , H01L45/1233 , H01L45/1273 , H01L45/146
摘要： A memristor includes a first electrode having a triangular cross section, in which the first electrode has a tip and a base, a switching material positioned upon the first electrode, and a second electrode positioned upon the switching material. The tip of the first electrode faces the second electrode and an active region in the switching material is formed between the tip of the first electrode and the second electrode.
摘要翻译： 忆阻器包括具有三角形横截面的第一电极，其中第一电极具有尖端和基部，位于第一电极上的开关材料和位于开关材料上的第二电极。 第一电极的尖端面对第二电极，并且开关材料中的有源区形成在第一电极的尖端和第二电极之间。
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公开(公告)号：US20130099872A1
公开(公告)日：2013-04-25
申请号：US13280808
申请日：2011-10-25
IPC分类号： H03B29/00
CPC分类号： G06F7/588
摘要： Chaotic oscillator-based random number generation is described. In an example, a circuit includes a negative differential resistance (NDR) device to receive an alternating current (AC) bias. The circuit further includes a capacitance in parallel with the NDR device, the capacitance having a value such that, in response to a direct current (DC) bias applied to the NDR device and the capacitance, a voltage across the capacitance oscillates with a chaotic period. The circuit further includes a random number generator to generate random numbers using samples of the voltage across the capacitance.
摘要翻译： 描述了基于混沌振荡器的随机数生成。 在一个示例中，电路包括用于接收交流（AC）偏压的负差分电阻（NDR）装置。 电路还包括与NDR器件并联的电容，该电容具有这样的值，使得响应于施加到NDR器件的直流（DC）偏压和电容，电容两端的电压以混沌周期 。 电路还包括随机数发生器，以使用电容两端的电压样本来产生随机数。
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