公开(公告)号：US20220059508A1

公开(公告)日：2022-02-24

申请号：US17520568

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H05K1/02

Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy across the substrate. The thermal energy is transferred from the semiconductor device to the graphene layer using one or more thermal connectors.

公开(公告)号：US20210118852A1

公开(公告)日：2021-04-22

申请号：US16939756

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/66 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01Q1/48 ,  H01Q1/22

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20190273000A1

公开(公告)日：2019-09-05

申请号：US16418091

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L21/447 ,  H01L21/687

Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.

公开(公告)号：US20190214331A1

公开(公告)日：2019-07-11

申请号：US16351816

申请日：2019-03-13

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Eiichi Nakano

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L41/047 ,  H01R12/77

Abstract: A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate.

公开(公告)号：US20190198443A1

公开(公告)日：2019-06-27

申请号：US16182901

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/48 ,  H05K1/11

Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.

公开(公告)号：US10319696B1

公开(公告)日：2019-06-11

申请号：US15976398

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L21/44 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78 ,  H01L21/683

Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.

公开(公告)号：US20190172724A1

公开(公告)日：2019-06-06

申请号：US15828819

申请日：2017-12-01

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L21/447 ,  H01L21/687

CPC classification number: H01L21/447 ,  H01L21/68778 ,  H01L21/68785 ,  H01L22/20 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2225/1094 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/83

Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.

公开(公告)号：US10217726B1

公开(公告)日：2019-02-26

申请号：US15693039

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00

Abstract: Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. In some embodiments, a semiconductor device comprises a substrate, a first die mounted to the substrate and including first inductors, and a second die mounted to the first die in an offset position and including second inductors. The first inductors are at an active side of the first die, and the second inductors are at an active side of the second die. At least a portion of the first inductors are proximate and inductively coupled to the second inductors. The semiconductor device further comprises a first plurality of interconnects electrically coupling the substrate to the first die, and a second plurality of interconnects electrically coupling the second die to the substrate. The first plurality of interconnects extend from an upper surface of the substrate to the active side of the first die, and the second plurality of interconnects extend from the active side of the second die to the lower surface of the substrate.