公开(公告)号：US12131178B2

公开(公告)日：2024-10-29

申请号：US18054858

申请日：2022-11-11

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/455 ,  G06F9/4401 ,  G06F12/1009 ,  G06F9/48 ,  G06F13/10

CPC classification number: G06F9/45558 ,  G06F9/4401 ,  G06F9/4403 ,  G06F12/1009 ,  G06F9/485 ,  G06F13/102

Abstract: Systems, apparatuses, and methods related to a hypervisor status register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store a value in the hypervisor status register during a power up process of the computer system. The value stored in the hypervisor status register that identifies whether or not an operating hypervisor is present in the computer system. The computer processor can configure its operations (e.g., address translation) based on the value stored in the hypervisor status register.

公开(公告)号：US12019555B2

公开(公告)日：2024-06-25

申请号：US17836912

申请日：2022-06-09

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/0864 ,  G06F9/30 ,  G06F9/38 ,  G06F13/16

CPC classification number: G06F12/0864 ,  G06F9/30098 ,  G06F9/3842 ,  G06F13/1684 ,  G06F2212/6042

Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

公开(公告)号：US11907158B2

公开(公告)日：2024-02-20

申请号：US17135465

申请日：2020-12-28

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F15/80 ,  G06F7/57 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F15/8076 ,  G06F7/57 ,  G06F9/30101

Abstract: A vector processor with a vector first and multi-lane configuration. A vector operation for a vector processor can include a single vector or multiple vectors as input. Multiple lanes for the input can be used to accelerate the operation in parallel. And, a vector first configuration can enhance the multiple lanes by reducing the number of elements accessed in the lanes to perform the operation in parallel.

公开(公告)号：US11868274B2

公开(公告)日：2024-01-09

申请号：US17341988

申请日：2021-06-08

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F21/00 ,  G06F12/14 ,  G06F12/1018 ,  G06F21/79 ,  G06F21/60 ,  H04L9/08 ,  G06F21/71

CPC classification number: G06F12/1408 ,  G06F12/1018 ,  G06F12/1475 ,  G06F21/602 ,  G06F21/71 ,  G06F21/79 ,  H04L9/0861 ,  H04L9/0894 ,  G06F2212/1052

Abstract: Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a secure zone configured to store keys and an unscrambled zone configured to operate on unscrambled data. The processor can convert the scrambled data into the unscrambled data in the unscrambled zone using the keys retrieved from the secure zone in response to execution of instructions configured to operate on the unscrambled data. Another processor may also be coupled with the memory, but can be prevented from accessing the unscrambled data in the unscrambled zone.

公开(公告)号：US11681594B2

公开(公告)日：2023-06-20

申请号：US17738986

申请日：2022-05-06

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F11/26 ,  G06F11/22 ,  G06F9/30

CPC classification number: G06F11/26 ,  G06F9/3001 ,  G06F9/30036 ,  G06F11/2236

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

公开(公告)号：US20230146488A1

公开(公告)日：2023-05-11

申请号：US18148701

申请日：2022-12-30

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/34 ,  G06F12/10 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/34 ,  G06F12/10 ,  G06F9/30043 ,  G06F2212/657 ,  G06F2212/1008

Abstract: A system, method and apparatus to facilitate data exchange via pointers. For example, in a computing system having a first processor and a second processor that is separate and independent from the first processor, the first processor can run a program configured to use a pointer identifying a virtual memory address having an ID of an object and an offset within the object. The first processor can use the virtual memory address to store data at a memory location in the computing system and/or identify a routine at the memory location for execution by the second processor. After the pointer is communicated from the first processor to the second processor, the second processor can access the same memory location identified by the virtual memory address. The second processor may operate on the data stored at the memory location or load the routine from the memory location for execution.

公开(公告)号：US11620239B2

公开(公告)日：2023-04-04

申请号：US17154722

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/14 ,  G06F12/10 ,  G06F21/53

Abstract: Systems, apparatuses, and methods related to a domain register of a processor in a computer system are described. The computer system has a memory configured to at least store instructions of routines that are classified in multiple predefined, non-hierarchical domains. The processor stores in the domain register an identifier of a current domain of a routine that is being executed in the processor. The processor is configured to perform security operations based on the content of the domain register and the security settings specified respectively for the predefined, non-hierarchical domains.

公开(公告)号：US11544069B2

公开(公告)日：2023-01-03

申请号：US16170799

申请日：2018-10-25

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/34 ,  G06F12/10

Abstract: A system, method and apparatus to facilitate data exchange via pointers. For example, in a computing system having a first processor and a second processor that is separate and independent from the first processor, the first processor can run a program configured to use a pointer identifying a virtual memory address having an ID of an object and an offset within the object. The first processor can use the virtual memory address to store data at a memory location in the computing system and/or identify a routine at the memory location for execution by the second processor. After the pointer is communicated from the first processor to the second processor, the second processor can access the same memory location identified by the virtual memory address. The second processor may operate on the data stored at the memory location or load the routine from the memory location for execution.

公开(公告)号：US20220414019A1

公开(公告)日：2022-12-29

申请号：US17899366

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/1009 ,  G06F12/14 ,  G11C11/16 ,  G06F9/455 ,  G11C8/20

Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

公开(公告)号：US20220391212A1

公开(公告)日：2022-12-08

申请号：US17888410

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/0891

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.