摘要:
A call is placed to a communications device. A response to the call is received from a call recipient associated with the communications device. The received response is processed based on a set of parameters. Based on processing the received response, a determination is made whether the call recipient is a human or an answering machine. If the call recipient is determined to be a human, the call is handled in a first manner. If the call recipient is determined to be an answering machine, the call is handled in a second manner that is different from the first manner.
摘要:
A base station (BS) which communicates with a plurality of mobile stations (MSs) is configured so as to comprise a control signal generation unit which generates control signals showing information on the allocation of resources for each of the plurality of mobile stations (MSs), and a transmission unit which transmits the control signals to the plurality of mobile stations (MSs). A control signal for a given mobile station (MS) includes information relating to another mobile station (MS).
摘要:
Disclosed is a current compensation circuit. During calibration of a compensation current, a digital control circuit delivers a digital signal with values varying over time to a current compensation array, the current compensation array outputs different amounts of compensation current based on the digital signal with values varying over time, the digital control circuit latches a value of the digital signal, which results in a best compensation current, based on influences of the different amounts of compensation current on a parameter to be calibrated, to complete the calibration. Upon and after completion of the calibration, the digital control circuit continuously delivers the digital signal with the latched value to the current compensation array, and the current compensation array outputs the best compensation current based on the digital signal with the latched value.
摘要:
A maximum voltage selection circuit and method and a sub-selection circuit are provided. The maximum voltage selection circuit includes a peripheral signal circuit and a selection circuit with N channels of input voltages. The peripheral signal circuit provides an operating mode signal and a reference voltage to the selection circuit including N sub-selection circuits coupled to the N channels of input voltages respectively. A sub-selection circuit determines its operating mode according to the operating mode signal. In the operating mode, when an input voltage of a sub-selection circuit is larger than the reference voltage, the sub-selection circuit sets itself to the output enable state and sets other sub-selection circuits to the output disable state, and outputs its input voltage as a maximum voltage through a PMOS.
摘要:
A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an A/D conversion circuit, an input signal circuit generates an input signal to the A/D conversion circuit, the A/D conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs
摘要:
The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to VGate1 when the voltage of the high-potential terminal is lower than a first pre-set value V1, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to VGate2 when the voltage of the low-potential terminal is higher than a second pre-set value V2, wherein the voltages of the first stage output of the comparator are between VGND and VCC. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved.
摘要:
Provided herein are modified anti-EGFR antibodies and nucleic acid molecules encoding modified anti-EGFR antibodies. Also provided are methods of treatment and uses using modified anti-EGFR antibodies.
摘要:
Apparatus and methods for a power-on-reset (POR) circuit are provided. In an example, a (POR) circuit can include a self-bias module configured to provide a reference voltage, a feedback module configured to provide a feedback voltage, a comparison module configured to compare the feedback voltage to the reference voltage and to provide an output signal, an inverter configured to couple the output of the comparison module to an enable input of the self-bias module, and a switch module coupled to the inverter, wherein the switch module and the inverter are configured to disabled the self bias module when the feedback voltage exceeds the reference voltage.
摘要:
Methods and diagnostic agents for identification of subjects for cancer treatment with an anti-hyaluronan agent, such as a hyaluronan-degrading enzyme, are provided. Diagnostic agents for the detection and quantification of hyaluronan in a biological sample and monitoring cancer treatment with an anti-hyaluronan agent, for example a hyaluronan-degrading enzyme, are provided. Combinations and kits for use in practicing the methods also are provided.
摘要:
A user equipment for performing effective coding scheme of uplink control information transmission is provided. The user equipment transmits, to a base station apparatus, channel state information for multiple downlink component carriers, the user equipment comprising: a determining unit for determining, the number of coded symbol for the channel state information for multiple downlink component carriers, using the number of bits, which is obtained by concatenating channel state information bits for each downlink component carrier and attaching Cyclic Redundancy Check (CRC) bits to the concatenated channel state information bits for each downlink component carrier.