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公开(公告)号：US06462416B1
公开(公告)日：2002-10-08
申请号：US09905469
申请日：2001-07-13
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening formed therein is formed on the semiconductor substrate. A barrier layer of barrier metal and barrier compound lines the opening, the barrier layer having a dielectric layer proximate and distal regions. The barrier layer has no barrier metal adjacent the dielectric layer proximate region and all barrier metal in the dielectric layer distal region, the barrier layer has all barrier compound adjacent the dielectric layer proximate region and no barrier compound before the dielectric layer distal region. A conductor core is over the barrier layer fills the opening and connects to the semiconductor device.
摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 其中形成有开口的器件介电层形成在半导体衬底上。 势垒金属和屏障化合物的阻挡层划分开口，阻挡层具有接近和远端区域的电介质层。 阻挡层在电介质层邻近区域附近没有阻挡金属，并且介电层远侧区域中的所有势垒金属，阻挡层具有邻近电介质层邻近区域的所有阻挡化合物，并且在电介质层远端区域之前没有阻挡化合物。 阻挡层之上的导体芯填充开口并连接到半导体器件。
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公开(公告)号：US06462409B1
公开(公告)日：2002-10-08
申请号：US09876259
申请日：2001-06-06
IPC分类号： H01L2314
CPC分类号： B24B37/107 , B24B21/04 , H01L21/3212
摘要： A semiconductor wafer polishing method and apparatus therefor are provided having a system housing and a robotic handling system for moving the semiconductor wafer between a belt module and a rotary module for respective linear and rotary polishing. A buff module and a cleaning module are provided in the system housing for buffing and cleaning the semiconductor wafer.
摘要翻译： 提供了一种半导体晶片抛光方法及其装置，具有系统壳体和用于在半导体晶片之间移动半导体晶片的机器人处理系统，用于相应的线性和旋转抛光。 在系统外壳中设置有一个抛光模块和一个清洁模块，用于抛光和清洁半导体晶片。
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公开(公告)号：US06440289B1
公开(公告)日：2002-08-27
申请号：US09285334
申请日：1999-04-02
IPC分类号： C25D712
CPC分类号： H01L21/76873 , C25D5/18 , C25D7/123 , H01L21/2885 , H01L21/76843 , H01L2221/1089
摘要： A method is provided of forming a semiconductor seed layer starting with a non-electrochemical deposition of an initial deposition of the seed layer. This is followed by a very slow deposition rate electrochemical deposition with an organic additive at the beginning of the plating process to overcome the initial thin seed coverage at the bottom and bottom sidewall of a feature. The electrochemical deposition plates at a very low rate initially followed by a low rate deposition to build up a thicker and more uniform seed layer at the bottom and bottom sidewall. In the meantime, this slow plating rate step only adds a small thickness to the top portion of the feature where non-electrochemical deposition seed coverage was initially thicker.
摘要翻译： 提供一种形成半导体种子层的方法，其以非电化学沉积种子层的初始沉积开始。 其次是在电镀工艺开始时用有机添加剂进行非常缓慢的沉积速率的电化学沉积，以克服特征底部和底部侧壁处的初始薄种子覆盖。 电化学沉积板以非常低的速率开始，随后是低速沉积，以在底部和底部侧壁处建立更厚和更均匀的种子层。 同时，这种缓慢电镀速率步骤仅在非电化学沉积种子覆盖率最初较厚的特征的顶部部分增加了小的厚度。
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64.发明授权公开(公告)号：US06425991B1
公开(公告)日：2002-07-30
申请号：US09678182
申请日：2000-10-02
IPC分类号： C25D1700
CPC分类号： H01L21/2885 , C25D7/123 , C25D17/001
摘要： An electroplating system is provided for seed layer covered semiconductor wafers. A plating chamber is provided with an inert primary anode connectible to a positive voltage source and a semiconductor wafer connector connectible to a negative voltage source. The plating chamber further contains a consumable ring secondary anode connectible to the positive voltage source such that, when the plating chamber is filled with a plating solution and a semiconductor wafer is connected to the semiconductor wafer connector and the voltages are connected, the seed layer on the semiconductor wafer will be plated by consuming the consumable ring secondary anode.
摘要翻译： 为种子层覆盖的半导体晶片提供电镀系统。 电镀室设置有可连接到正电压源的惰性主阳极和可连接到负电压源的半导体晶片连接器。 电镀室还包括可连接到正电压源的消耗环次级阳极，使得当电镀室中填充有镀液并且半导体晶片连接到半导体晶片连接器并且电压被连接时，种子层在 半导体晶片将通过消耗消耗环次级阳极进行电镀。
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公开(公告)号：US06228768B1
公开(公告)日：2001-05-08
申请号：US09184009
申请日：1998-11-02
IPC分类号： H01L21302
CPC分类号： H01L21/67109 , H01L21/288 , H01L21/2885 , H01L21/67769 , H01L21/76877
摘要： Cu metalized wafers are stored at elevated temperatures to substantially complete recrystalization, thereby enabling subsequent CMP with a high degree of wafer to wafer uniformity. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill one or more damascene openings in a plurality of wafers, placing the wafers in one or more cassettes, and storage-annealing the cassettes on shelves of a cabinet maintained at about 50° C. to about 200° C. in nitrogen for about 2 minutes to about 3 days.
摘要翻译： Cu金属化晶片在升高的温度下储存以实质上完全重结晶，从而使后续CMP具有高度的晶片与晶片的均匀性。 实施例包括电镀或无电镀Cu或Cu合金以填充多个晶片中的一个或多个镶嵌开口，将晶片放置在一个或多个盒中，以及将盒保存在保持在约50℃的柜的架上 至约200℃在氮气中约2分钟至约3天。
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66.发明授权
公开(公告)号：US6096648A
公开(公告)日：2000-08-01
申请号：US237584
申请日：1999-01-26
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76886 , H01L21/76819 , H01L21/76835 , H01L21/76837 , H01L21/76885
摘要： A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.
摘要翻译： 一种用包括嵌入的低介电常数层的铜对半导体芯片进行金属化的方法。 该方法包括在半导体芯片的表面上沉积阻挡层的步骤。 接下来，在阻挡层上沉积铜籽晶层，然后对铜籽晶层进行退火。 然后在半导体芯片上进行微光刻，以形成具有图案化光致抗蚀剂层的多条布线路径。 在形成布线路径之后，将铜导电层电镀到半导体芯片的表面。 接下来，将图案化的光致抗蚀剂层剥离出半导体芯片的表面。 此外，也去除了被图案化光致抗蚀剂层覆盖的阻挡层和铜籽晶层的部分。 然后在半导体芯片上沉积低介电常数层以填充新生成的铜导线之间的间隙。
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67.发明授权Point of use mixing for LI/plug tungsten polishing slurry to improve existing slurry 失效使用点混合为LI /塞钨抛光浆料改善现有浆料
公开(公告)号：US6017463A
公开(公告)日：2000-01-25
申请号：US976026
申请日：1997-11-21
CPC分类号： B24B37/044 , C09G1/02 , C09K3/1409 , C09K3/1463 , H01L21/3212 , H01L21/76895 , H01L23/53257 , H01L2924/0002
摘要： An improved tungsten plug/Local Interconnect slurry for Chemical Mechanical Polishing which does not require inclusion of a chemical stabilizer. The slurry is made using a combination of two separate batch mixings of stable ingredients and Point-of Use mixing of portions of the two batches, whereby the oxidizers are combined with the coated abrasive mixture immediately prior to dispensing the slurry onto the polishing pad by combining selected flows from each of the two batches to form a total flow rate equal to the required rate of slurry flow onto the polishing pad.
摘要翻译： 用于化学机械抛光的改进的钨丝塞/局部互连浆料，不需要包含化学稳定剂。 浆料是使用两种分批的混合批料混合物的组合制成的，其中两批分批混合的两批次的部分混合，由此在将浆料分配到抛光垫上之前将氧化剂与涂覆的磨料混合物组合 从两个批次中的每一个选择的流量形成等于浆料流入抛光垫的所需速率的总流量。
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公开(公告)号：US07994047B1
公开(公告)日：2011-08-09
申请号：US11286173
申请日：2005-11-22
IPC分类号： H01L23/485
CPC分类号： H01L23/5226 , H01L21/2855 , H01L21/76843 , H01L21/76865 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit contact system is provided including forming a contact plug in a dielectric and forming a first barrier layer in a trench in the dielectric and on the contact plug. Further, the system includes removing a portion of the first barrier layer from the bottom of the first barrier layer and depositing the portion of the first barrier layer on the sidewall of the first barrier layer, and forming a second barrier layer over the first barrier layer and filling a corner area of the trench.
摘要翻译： 提供了一种集成电路接触系统，包括在电介质中形成接触插塞并在电介质和接触插塞中的沟槽中形成第一阻挡层。 此外，该系统包括从第一阻挡层的底部去除第一阻挡层的一部分，并将第一阻挡层的该部分沉积在第一阻挡层的侧壁上，以及在第一阻挡层上形成第二阻挡层 并填充沟槽的一个角落区域。
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69.发明授权Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration 有权复合钽封装铜，具有减少的电迁移和减少的应力迁移公开(公告)号：US07071564B1
公开(公告)日：2006-07-04
申请号：US10791904
申请日：2004-03-04
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L2924/0002 , H01L2924/00
摘要： The electromigration and stress migration of Cu interconnects is significantly reduced by forming a composite capping layer comprising a layer of β-Ta on the upper surface of the inlaid Cu, a layer of tantalum nitride on the β-Ta layer and a layer of α-Ta on the tantalum nitride layer. Embodiments include forming a recess in an upper surface of Cu inlaid in a dielectric layer, depositing a layer of β-Ta at a thickness of 25 Å to 40 Å, depositing a layer of tantalum nitride at a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å. Embodiments further include forming an overlying dielectric layer, forming an opening therein, e.g., a via opening or a dual damascene opening, lining the opening with α-Ta, and filling the opening with Cu in electrical contact with the underlying inlaid Cu.
摘要翻译： 通过在嵌入的Cu的上表面上形成包含β-Ta层的复合顶盖层，β-Ta层上的氮化钽层和α-Ta层的一层复合覆盖层，显着降低了铜互连的电迁移和应力迁移， Ta在氮化钽层上。 实施例包括在介电层中嵌入的Cu的上表面中形成凹陷，沉积厚度为的Å-Ta层，沉积厚度为Å至100埃的氮化钽层，以及 然后沉积厚度为200埃至500埃的α-Ta层。 实施例还包括形成覆盖的介电层，在其中形成开口，例如通孔开口或双镶嵌开口，用α-Ta衬套开口，以及用与电镀底层Cu接触的Cu填充开口。
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70.发明授权Method for forming conductor reservoir volume for integrated circuit interconnects 有权用于形成集成电路互连的导体储存器容积的方法公开(公告)号：US06939803B2
公开(公告)日：2005-09-06
申请号：US10225656
申请日：2002-08-21
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76838 , H01L21/76873 , H01L21/76874 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.
摘要翻译： 提供了具有半导体器件的半导体衬底的集成电路及其制造方法。 在半导体衬底上形成器件电介质层。 器件介电层上的第一介电层具有形成在其中的开口，其中包括导体储存器体积。 屏障层对通道开口进行排列。 导体芯填充阻挡层上的开口。 第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。 除了第一通道开口之外，阻挡层沿着第二通道和通孔开口。 导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。 导体储存器容积提供导体材料供应，以防止在第一通道和通孔中形成空隙。
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